NVIC寄存器

stm32_exti（含NVIC）配置及库函数讲解2013-03-0321:37:30|分类：STM32F103VBT6|标签：stm32_extistm32_nvic|举报|字号订阅EXTIexternalinterrupt外部中断STM32有76个中断，包括16个内核中断和60个可屏蔽中断，具有16级可编程的中断优先级。而我们常用的就是这60个可屏蔽中断，所以我们就只针对这60个可屏蔽中断进行介绍。关于中断的设置，在STM32的PDF文档中是找不到关于NVIC相关寄存器的说明的，是让大家摸不着门道吗？还是故装高深？最后在《CM3权威指南》上找到NVIC相关寄存器，下面重点介绍这几个寄存器。ISER[2]：ISER全称是InterruptSet-EnableRegisters，这是一个中断使能寄存器组。上面说了STM32的可屏蔽中断只有60个，这里用了2个32位的寄存器，总共可以表示64个中断。而STM32只用了其中的前60个。ISER[0]的bit0~bit31分别对应中断0~31。ISER[1]的bit0~bit27对应中断32~59；这样总共60个中断就分别对应上了。你要使能某个中断，必须设置相应的ISER位为1，使该中断被使能（这里仅仅是使能，还要配合中断分组、屏蔽、IO口映射等设置才算是一个完整的中断设置）。具体每一位对应哪个中断，请参考stm32f10x_nvic.h里面的第36行处。/*IRQChannels--------------------------------------------------------------*/#defineWWDG_IRQChannel((u8)0x00)/*WindowWatchDogInterrupt*/#definePVD_IRQChannel((u8)0x01)/*PVDthroughEXTILinedetectionInterrupt*/#defineTAMPER_IRQChannel((u8)0x02)/*TamperInterrupt*/#defineRTC_IRQChannel((u8)0x03)/*RTCglobalInterrupt*/#defineFLASH_IRQChannel((u8)0x04)/*FLASHglobalInterrupt*/#defineRCC_IRQChannel((u8)0x05)/*RCCglobalInterrupt*/#defineEXTI0_IRQChannel((u8)0x06)/*EXTILine0Interrupt*/#defineEXTI1_IRQChannel((u8)0x07)/*EXTILine1Interrupt*/#defineEXTI2_IRQChannel((u8)0x08)/*EXTILine2Interrupt*/#defineEXTI3_IRQChannel((u8)0x09)/*EXTILine3Interrupt*/#defineEXTI4_IRQChannel((u8)0x0A)/*EXTILine4Interrupt*/#defineDMA1_Channel1_IRQChannel((u8)0x0B)/*DMA1Channel1globalInterrupt*/#defineDMA1_Channel2_IRQChannel((u8)0x0C)/*DMA1Channel2globalInterrupt*/#defineDMA1_Channel3_IRQChannel((u8)0x0D)/*DMA1Channel3globalInterrupt*/#defineDMA1_Channel4_IRQChannel((u8)0x0E)/*DMA1Channel4globalInterrupt*/#defineDMA1_Channel5_IRQChannel((u8)0x0F)/*DMA1Channel5globalInterrupt*/#defineDMA1_Channel6_IRQChannel((u8)0x10)/*DMA1Channel6globalInterrupt*/#defineDMA1_Channel7_IRQChannel((u8)0x11)/*DMA1Channel7globalInterrupt*/#defineADC1_2_IRQChannel((u8)0x12)/*ADC1etADC2globalInterrupt*/#defineUSB_HP_CAN_TX_IRQChannel((u8)0x13)/*USBHighPriorityorCANTXInterrupts*/#defineUSB_LP_CAN_RX0_IRQChannel((u8)0x14)/*USBLowPriorityorCANRX0Interrupts*/#defineCAN_RX1_IRQChannel((u8)0x15)/*CANRX1Interrupt*/#defineCAN_SCE_IRQChannel((u8)0x16)/*CANSCEInterrupt*/#defineEXTI9_5_IRQChannel((u8)0x17)/*ExternalLine[9:5]Interrupts*/#defineTIM1_BRK_IRQChannel((u8)0x18)/*TIM1BreakInterrupt*/#defineTIM1_UP_IRQChannel((u8)0x19)/*TIM1UpdateInterrupt*/#defineTIM1_TRG_COM_IRQChannel((u8)0x1A)/*TIM1TriggerandCommutationInterrupt*/#defineTIM1_CC_IRQChannel((u8)0x1B)/*TIM1CaptureCompareInterrupt*/#defineTIM2_IRQChannel((u8)0x1C)/*TIM2globalInterrupt*/#defineTIM3_IRQChannel((u8)0x1D)/*TIM3globalInterrupt*/#defineTIM4_IRQChannel((u8)0x1E)/*TIM4globalInterrupt*/#defineI2C1_EV_IRQChannel((u8)0x1F)/*I2C1EventInterrupt*/#defineI2C1_ER_IRQChannel((u8)0x20)/*I2C1ErrorInterrupt*/#defineI2C2_EV_IRQChannel((u8)0x21)/*I2C2EventInterrupt*/#defineI2C2_ER_IRQChannel((u8)0x22)/*I2C2ErrorInterrupt*/#defineSPI1_IRQChannel((u8)0x23)/*SPI1globalInterrupt*/#defineSPI2_IRQChannel((u8)0x24)/*SPI2globalInterrupt*/#defineUSART1_IRQChannel((u8)0x25)/*USART1globalInterrupt*/#defineUSART2_IRQChannel((u8)0x26)/*USART2globalInterrupt*/#defineUSART3_IRQChannel((u8)0x27)/*USART3globalInterrupt*/#defineEXTI15_10_IRQChannel((u8)0x28)/*ExternalLine[15:10]Interrupts*/#defineRTCAlarm_IRQChannel((u8)0x29)/*RTCAlarmthroughEXTILineInterrupt*/#defineUSBWakeUp_IRQChannel((u8)0x2A)/*USBWakeUpfromsuspendthroughEXTILineInterrupt*/#defineTIM8_BRK_IRQChannel((u8)0x2B)/*TIM8BreakInterrupt*/#defineTIM8_UP_IRQChannel((u8)0x2C)/*TIM8UpdateInterrupt*/#defineTIM8_TRG_COM_IRQChannel((u8)0x2D)/*TIM8TriggerandCommutationInterrupt*/#defineTIM8_CC_IRQChannel((u8)0x2E)/*TIM8CaptureCompareInterrupt*/#defineADC3_IRQChannel((u8)0x2F)/*ADC3globalInterrupt*/#defineFSMC_IRQChannel((u8)0x30)/*FSMCglobalInterrupt*/#defineSDIO_IRQChannel((u8)0x31)/*SDIOglobalInterrupt*/#defineTIM5_IRQChannel((u8)0x32)/*TIM5globalInterrupt*/#defineSPI3_IRQChannel((u8)0x33)/*SPI3globalInterrupt*/#defineUART4_IRQChannel((u8)0x34)/*UART4globalInterrupt*/#defineUART5_IRQChannel((u8)0x35)/*UART5globalInterrupt*/#defineTIM6_IRQChannel((u8)0x36)/*TIM6globalInterrupt*/#defineTIM7_IRQChannel((u8)0x37)/*TIM7globalInterrupt*/#defineDMA2_Channel1_IRQChannel((u8)0x38)/*DMA2Channel1globalInterrupt*/#defineDMA2_Channel2_IRQChannel((u8)0x39)/*DMA2Channel2globalInterrupt*/#defineDMA2_Channel3_IRQChannel((u8)0x3A)/*DMA2Channel3globalInterrupt*/#defineDMA2_Channel4_5_IRQChannel((u8)0x3B)/*DMA2Channel4andDMA2Channel5globalInterrupt*/例如：EXTI9所对应的中断号为23。ICER[2]：全称是InterruptClear-EnableRegisters，是一个中断除能寄存器组。该寄存器组与ISER的作用恰好相反，是用来清除某个中断的使能的。这里要与专门设置一个ICER来清除中断位，而不是向ISER写0来清除，是因为NVIC的这些寄存器都是写1有效的，写0无效的。具体为什么这么设计，请看《CM3权威指南》第125页。ISPR[2]：全称是InterruptSet-PendingRegisters，是一个中断挂起控制寄存器组。每一位对应的中断和ISER是一样的。通过置1，可以将正在进行的中断挂起，而执行同级或更高级别的中断。写0是无效的。ICPR[2]：全称是:InterruptClear-PendingRegisters，是一个中断解挂控制寄存器组。其作用与ISPR相反，对应位也和ISER是一样的。通过设置1，可以将挂起的中断解挂。写0无效。IABR[2]：全称是ActiveBitRegisters，是一个中断激活标志位寄存器组。对应位所代表的的中断和ISER一样，如果为1，则表示该位所对应的中断正在被执行。这是一个只读寄存器，通过它可以知道当前在执行的中断是哪一个。在中断执行完了由硬件自动清零。IPR[15]：全称是InterruptPrior