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ofSheetDate:Title:Ver:ABCD1234DCBA4321SheetSize:BRev:DrawnByDNPSwitcherPage12Page9AudioAC97Optional10/100/1000PHYRJ45MagneticsIICEEPROMGeneratorGlockVirtex5Page9HeadersforSystemMonPage12Page6PS2Keybaord&MousePage12SystemACEPage7USBHost&PeripheralZBTSRAMLinearFlashUSERClock2lineCharacterLCDPage12UARTPage12GPIOPage10DVIConnPage16CodecPage15Page1364BitDDR2SODIMMPlatformFlashU4TDOTDITDIPC4TDITSTTDITDI2.5V@3Amax2.5V@3AmaxPWRJackLinearSwitcherLinearSwitcher0.9V@1.4AmaxTDITDOTDOCFGTDOTDOExpansionJ21FPGAU1U2U3CPLDPlatformFlashJ1TDOCFGTDITSTTDOJTAGChainPage9DiffSMAClocksExpansionHeaderPage11SATA,SFPandSGMIIIICSPIFLASHPage8PlatformFLASHVideoInCodecPage17Page8Switcher3.3V@10Amax1.8V@10Amax1.0V@16Amax1.0V@3.0Amax1.2V@3.0AmaxLinear-MGTAVTTTXLinear-MGTAVCCLinearMGTPLLLinear-MGTAVTTRX1.2V@3Amax1.2V@3AmaxLinear-VCCAUX5.0V@10AmaxDebugMictor,TraceSofTouchSystemACECFPage22-24Page20Page20Page21J5U5Page15Page18Page11Page25-26R63Page19PC4CPLD-XC95144XLPowerSupplySCHEM,ROHSCOMPLIANT0381241GTPs5VML505/6/7BlockDiagramML505/6/7VIRTEX-5EVALUATIONPLATFORM,1280415Page2-6LXT/SXT/FXTA1-22-2008_14:5127102BPVCC3V3VCC3V3VCC3V3VCC3V3VCC2V5VCC3V3VCCO2_4VCCO1_4IO_L9N_CC_GC_4IO_L9P_CC_GC_4IO_L8N_CC_GC_4IO_L8P_CC_GC_4IO_L7N_GC_VRP_4IO_L7P_GC_VRN_4IO_L6N_GC_4IO_L6P_GC_4IO_L5N_GC_4IO_L5P_GC_4IO_L4N_GC_VREF_4IO_L4P_GC_4IO_L3P_GC_D9_4IO_L2P_GC_D11_4IO_L1P_GC_D13_4IO_L0P_GC_D15_4IO_L1N_GC_D12_4IO_L0N_GC_D14_4IO_L2N_GC_D10_4IO_L3N_GC_D8_4FF1136BANK4GNDA_FPGAVCC3V3VCCO2_3VCCO1_3IO_L9N_GC_3IO_L9P_GC_3IO_L8N_GC_3IO_L8P_GC_3IO_L7N_GC_3IO_L7P_GC_3IO_L6N_GC_3IO_L6P_GC_3IO_L5N_GC_3IO_L5P_GC_3IO_L4N_GC_VREF_3IO_L4P_GC_3IO_L3N_GC_3IO_L3P_GC_3IO_L2N_GC_VRP_3IO_L2P_GC_VRN_3IO_L1N_CC_GC_3IO_L1P_CC_GC_3IO_L0N_CC_GC_3IO_L0P_CC_GC_3FF1136BANK3VCCO2_1VCCO1_1IO_L9P_CC_A1_D17_1IO_L8P_CC_A3_D19_1IO_L7P_A5_D21_1IO_L6P_A7_D23_1IO_L5P_A9_D25_1IO_L4P_A11_D27_1IO_L3P_A13_D29_1IO_L2P_A15_D31_1IO_L1P_A17_1IO_L0P_A19_1IO_L0N_A18_1IO_L1N_A16_1IO_L2N_A14_D30_1IO_L3N_A12_D28_1IO_L4N_VREF_A10_D26_1IO_L5N_A8_D24_1IO_L6N_A6_D22_1IO_L7N_A4_D20_1IO_L8N_CC_A2_D18_1IO_L9N_CC_A0_D16_1FF1136BANK1IO_L9N_D0_FS0_2IO_L9P_D1_FS1_2IO_L8N_D2_FS2_2IO_L8P_D3_2IO_L7N_D4_2IO_L7P_D5_2IO_L6N_D6_2IO_L6P_D7_2IO_L5N_CSO_B_2IO_L5P_FWE_B_2IO_L4N_VREF_FOE_B_MOSI_2IO_L4P_FCS_B_2IO_L3N_A20_2IO_L3P_A21_2IO_L2N_A22_2IO_L2P_A23_2IO_L1N_CC_A24_2IO_L1P_CC_A25_2IO_L0N_CC_RS0_2IO_L0P_CC_RS1_2VCCO2_2VCCO1_2BANK2FF1136VCCO2_0VCCO1_0TMS_0M1_0M2_0AVSS_0AVDD_0TDO_0M0_0TCK_0RSVD2_0RSVD1_0RDWR_B_0CS_B_0INIT_B_0CCLK_0DONE_0D_IN_0HSWAPEN_0PROGRAM_B_0VBATT_0VN_0VP_0DXN_0DXP_0VREFN_0VREFP_0D_OUT_BUSY_0TDI_0FF1136BANK0ofSheetDate:Title:Ver:ABCD1234DCBA4321SheetSize:BRev:DrawnByUnusedRP1Resistors3.3VVCC03.3VVCC03.3VVCC02.5VVCC03.3VVCC0Config,FLASH,SRAM,GPIO,CLKsBanks0,1,2,3,4FPGABanks0,1,2,3,4,SCHEM,ROHSCOMPLIANT0381241Config,FLASH,SRAM,GPIO,CLKsML505/6/7VIRTEX-5EVALUATIONPLATFORM,1280415A021-22-2008_14:51272BPGPIO_LED_4RESERVED2RESERVED1AD23AA22AC14AC22AD22T17T18AD14AD21AB15AC23AB23N23N22N14N15M15P15M23M22L23V17U18W17W18U17V18AD15AC15U1SG-BGA-604612J8021RP14.7K5%685%4.7KRP1AUDIO_SYNCAUDIO_BIT_CLKCLK_33MHZ_FPGACLK_27MHZ_FPGAUSER_CLK12R1601/16W5%FPGA_TDOFPGA_DONE12R23321%12R1DNP1%AD19AE19AE17AF16AD20AE21AE16AF15AF21AF20AF14AE14AE23AE22AG12AF13AG23AF23AE12AE13AH21AM19U1SG-BGA-6046K12H23H12K22K14H22J15K21L16L20L21L15J22K16G22L14K23J12G23K13D13G14U1SG-BGA-6046D23E20H20H19H13J14J21J20H15H14K19L19J17J16J19K18G16G15L18K17H18H17U1SG-BGA-604621C20.01UF16VX7R21C10.01UF16VX7R12R5DNP1%12R31%1.21K155%4.7KRP16105%4.7KRP196RP14.7K5%76RP14.7K5%41RP14.7K5%135%4.7KRP1FPGA_VREFPFPGA_AVDDFPGA_DIFF_CLK_OUT_NFPGA_DIFF_CLK_OUT_PSMA_DIFF_CLK_IN_NPHY_TXC_GTXCLKFPGA_CS0_BFPGA_INIT_BFPGA_SERIAL1_RXFPGA_SERIAL1_TXAG14AL12AG17AH18AE18AF18AG16AH17AF19AG18AG15AH15AG20AG21AH14AH20AH12AG22AG13AH22AH19AH13U1SG-BGA-6046211%DNPR712R9DNP1%12R64.75K1%211%4.75KR8211%4.75KR4SRAM_FLASH_D14SRAM_CLKPHY_TXCLKPHY_RXCLKGPIO_LED_1GPIO_LED_0FLASH_AUDIO_RESET_BAUDIO_SDATA_INAUDIO_SDATA_OUTSRAM_FLASH_D8SRAM_FLASH_D9SRAM_FLASH_D10SRAM_FLASH_D11SRAM_FLASH_D12SRAM_FLASH_D13SRAM_FLASH_D15GPIO_LED_2CLK_FPGA_NCLK_FPGA_PPHY_MDCPHY_INTPHY_MDIOPHY_RESETSMA_DIFF_CLK_IN_PFPGA_CS_BFPGA_M0FPGA_M2FPGA_M1FPGA_HSWAPENFPGA_RDWR_BFPGA_EXP_TCKFPGA_DINFPGA_EXP_TMSFLASH_CE_BFLASH_OE_BSRAM_FLASH_D2SRAM_FLASH_D1SRAM_FLASH_D0SRAM_FLASH_A21SRAM_FLASH_WE_BCFG_ADDR_OUT0CFG_ADDR_OUT1SRAM_FLASH_A20FPGA_V_NFPGA_V_PFPGA_DX_NFPGA_DX_PSRAM_FLASH_A0SRAM_FLASH_A19FPGA_PROG_BFPGA_VBATTFPGA_DOUT_BUSYFPGA_TDISRAM_FLASH_A10SRAM_FLASH_A11SRAM_FLASH_A12SRAM_FLASH_A13SRAM_FLASH_A17SRAM_FLASH_A18SRAM_FLASH_A9SRAM_FLASH_A8SRAM_FLASH_A7SRAM_FLASH_A5SRAM_FLASH_A14SRAM_FLASH_A15SRAM_FLASH_A6SRAM_FLASH_A16SRAM_FLASH_A4SRAM_FLASH_A1SRAM_FLASH_A2SRAM_FLASH_D7SRAM_FLASH_D6SRAM_FLASH_D5SRAM_FLASH_D4SRAM_FLASH_D3SRAM_FLASH_A3NCNCGPIO_LED_SGPIO_LED_NGPIO_LED_EGPIO_LED_WLCD_FPGA_RSCLKBUF_Q1_NCLKBUF_Q1_PFPGA_CCLK-RVGA_IN_DATA_CLK21C3120PF50VNPOFPGA_CLK-C12R171401%FPGA_CCLK12R104.75K1%VCC1V8VTTVREFVCC1V8VTTVREFVCC1V8VCC1V8VCC1V8VCC1V8IO_L19N_17VCCO2_17VCCO1_17IO_L19P_17IO_L18N_17IO_L18P_17IO_L17N_17IO_L17P_17IO_L16N_17IO_L16P_17IO_L15
本文标题:XILINX-virtex5系列原理图
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