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1122334455667788DDCCBBAAAltiumLimitedL3,12aRodboroughRdFrenchsForestNSWAustralia20862016/8/1819:22:25F:\20160323桌面\STM32M4V1.1\CPU.SchDocTitleSize:Number:Date:File:Revision:SheetofTime:A3PB0PB1PB2PB3PB4PB5PB6PB7PB8PB9PB10PB11PB12PB13PB14PB15PC0PC1PC2PC3PC4PC5PC6PC7PC8PC9PC10PC11PC12PC13PC14PC15PD0PD1PD2PD3PD4PD5PD6PD7PD8PD9PD10PD11PD12PD13PD14PD15PE0PE1PE2PE3PE4PE5PE6PE7PE8PE9PE10PE11PE12PE13PE14PE15PF0PF1PF2PF3PF4PF5PF6PS_CLKPS_DATPF9PF10PF11PF12PF13PF14PF15PG0PG1PG2PG3PG4PG5PG6PG7PG8PG9PG10PG11PG12PG13PG14PG15D1100nFC6D2GND1225MY222pFC822pFC7RESETVDDAGNDV3.3M2.2uFC92.2uFC10GNDVDDA1MR210KR1100nFC3S1GNDV3.3BOOT0100nFC14100nFC15100nFC16100nFC17100nFC18100nFC19100nFC13100nFC20100nFC21100nFC22100nFC12100nFC11V3.3MGNDV3.3MGNDV3.3GNDRESET1232.768KY110pFC510pFC4GNDFSMC_NBL0FSMC_NBL1FSMC_NE3FSMC_NOEFSMC_NWED0D1D2D3D4D5D6D7D8D9D10D11D12D13D14D15A0A1A2A3A4A5A6A7A8A9A10A11A12A13A14A15A16A17A18TFTLCDJTAGBOOTRESETPE2/TRACECK/FSMC_A231PE3/TRACED0/FSMC_A192PE4/TRACED1/FSMC_A203PE5/TRACED2/FSMC_A214PE6/TRACED3/FSMC_A225VBAT6PC13/RTC_AF17PC14/OSC32_IN8PC15/OSC32_OUT9PF0/FSMC_A010PF1/FSMC_A111PF2/FSMC_A212PF3/FSMC_A313PF4/FSMC_A414PF5/FSMC_A515VSS16VDD17PF6/ADC3_IN4/FSMC_NIORD18PF7/ADC3_IN5/FSMC_NREG19PF8/ADC3_IN6/FSMC_NIOWR20PF9/ADC3_IN7/FSMC_CD21PF10/FSMC_INTR22OSC_IN23OSC_OUT24NRST25PC0/OTG_HS_ULPI_STP/ADC123_IN1026PC1/ETH_MDC/ADC123_IN1127PC2/SPI2_MISO/I2S2ext_SD/ADC123_IN1228PC3/SPI2_MOSI/I2S2_SD/ETH_MII_TX_CLK/ADC123_IN1329VDD30VSSA31Vref+32VDDA33PA0/USART4_TX/ETH_MII_CRS/TIM2_CH1_ETR/TIM5_CH1/ADC123_IN0/WKUP34PA1/USART4_RX/ETH_RMII_REF_CLK/ETH_MII_RX_CLK/TIM5_CH2/TIMM2_CH2/ADC123_IN135PA2USART2_TX/TIM5_CH3/TIM9_CH1/TIM2_CH3/ETH_MDIO/ADC123_IN236PA3/USART2_RX/TIM5_CH4/TIM9_CH2/TIM2_CH4/ETH_MII_COL/ADC123_IN337VSS38VDD39PA4/SPI1_NSS/SPI3_NSS/USART2_CK/ADC12_IN4/DAC1_OUT40PA5/SPI1_SCK/TIM2_CH1_ETR/TIM8_CHIN/ADC12_IN5/DAC2_OUT41PA6/SPI1_MISO/TIM8_BKIN/TIM13_CH1/TIM3_CH1/ADC12_IN642PA7/SPI1_MOSI/TIM14_CH1/TIM3_CH2/ETH_MII_RX_DV/ADC12_IN743PC4/ETH_RMII_RX_D0/ETH_MII_RX_D0/ADC12_IN1444PC5/ETH_RMII_RX_D1/ETH_MII_RX_D1/ADC12_IN1545PB0/TIM3_CH3/ETH_MII_RXD2/TIM1_CH2N/ADC12_IN846PB1/IM3_CH4/TIM8_CH3N/ETH_MII_RXD3/OTG_HS_INTN/ADC12_IN947PB2/BOOT148PF11/DCM1_1249PF12/FSMC_A650VSS51VDD52PF13/FSMC_A753PF14/FSMC_A854PF15/FSMC_A955PG0/FSMC_A1056PG1/FSMC_A1157PE7/FSMC_D458PE8/FSMC_D559PE9/FSMC_D660VSS61VDD62PE10/FSMC_D763PE11/FSMC_D864PE12/FSMC_D965PE13/FSMC_D1066PE14/FSMC_D1167PE15/FSMC_D1268PB10/SPI2_SCK/I2C2_SCL/USART3_TX/ETH_MII_RX_ER/IM2_CH369PB11/I2C2_SDA/USART3_RX/ETH_RMII_TX_EN/ETH_MII_TX_EN70VDD72PB12/SPI2_NSS/USART3_CK/CAN2_RX/ETH_RMII_TXD0/ETH_MII_TXD073PB13/SPI2_SCK/I2S2_CK/CAN2_TX/ETH_RMII_TXD1/ETH_MII_TXD174PB14/SPI2_MISO/TIM12_CH1/USART3_RTS/I2S2ext_SD75PB15/SPI2_MOSI/TIM8_CH3N/TIM12_CH276PD8/FSMC_D13/USART3_TX77PD9/FSMC_D14/USART3_RX78PD10/FSMC_D15/USART3_CK79PD11/FSMC_A16/USART3_CTS80PD12/FSMC_A17/TIM4_CH1/USART3_RTS81PD13/FSMC_A18/TIM4_CH282VSS83VDD84PD14/FSMC_D0/TIM4_CH385PD15/FSMC_D1/TIM4_CH486PG2/FSMC_A1287PG3/FSMC_A1388PG4/FSMC_A1489PG5/FSMC_A1590PG6/FSMC_INT291PG7/FSMC_INT392PG893VSS94VDD95PC6/I2S2_MCK/TIM8_CH1/SDIO_D6/USART6_TX/TIM3_CH196PC7/I2S3_MCK/TIM8_CH2/SDIO_D7/USART6_RX/TIM3_CH297PC8/TIM8_CH3/SDIO_D0/TIM3_CH3/USART6_CK/DCMI_D298PC9/I2S_CKIN/TIM8_CH4/SDIO_D1/I2C3_SDA/TIM3_CH499PA8/MCO1/USART1_CK/TIM1_CH1/I2C3_SCL/OTG_FS_SOF100PA9/USART1_TX/TIM1_CH2/I2C3_SMBA/DCMI_D0/OTG_FS_VBUS101PA10/USART1_RX/TIM1_CH3/OTG_FS_ID/DCMI_D1102PA11/USART1_CTS/CAN1_RX/TIM1_CH4/OTG_FS_DM103PA12/USART1_RTS/CAN1_TX/TIM1_ETR/OTG_FS_DP104PA13/JTMS-SWDIO105VSS107VDD108PA14/JTCK-SWCLK109PA15/JTDI/SPI3_NSS/I2S3_WS/TIM2_CH1_ETR/SPI1_NSS110PC10/SPI3_SCK/I2S3_CK/UART4_TX/SDIO_D2/USART3_TX111PC11/UART4_RX/SPI3_MISO/SDIO_D3/USART3_RX/I2S3ext_SD112PC12/UART5_TX/SDIO_CK/SPI3_MOSI/I2S3_SD/USART3_CK113PD0/FSMC_D2/CAN1_RX114PD1/FSMC_D3/CAN1_TX115PD2/TIM3_ETR/UART5_RXSDIO_CMD/DCMI_D11116PD3/FSMC_CLK/USART2_CTS117PD4/FSMC_NOE/USART2_RTS118PD5/FSMC_NWE/USART2_TX119VSS120VDD121PD6/FSMC_NWAIT/USART2_RX122PD7/USART2_CK/FSMC_NE1/FSMC_NCE2123PG9/FSMC_NE2/FSMC_NCE3124PG10/FSMC_NCE4_1/FSMC_NE3125PG11/FSMC_NCE4_2126PG12/FSMC_NE4127PG13/FSMC_A24128PG14/FSMC_A25129VSS130VDD131PG15132PB3/JTDO/TRACESWO/SPI3_SCK/I2S3_CK/TIM2_CH2/SPI1_SCK133PB4/NJTRST/SPI3_MISO/TIM3_CH1/SPI1_MISO/I2S3ext_SD134PB5/I2C1_SMBA/CAN2_RX/ETH_PPS_OUT/TIM3_CH2/SPI1_MOSI/SPI3_MOSI/I2S135PB6/I2C1_SCL/TIM4_CH1/CAN2_TX/DCMI_D5/USART1_TX136PB7/I2C1_SDA/FSMC_NL/DCMI_VSYNC/USART1_RX/TIM4_CH2137BOOT0138PB8/TIM4_CH3/SDIO_D4/ETH_MII_TXD3/I2C1_SCL/CAN1_RX139PB9/SPI2_NSS/I2S2_WS/TIM4_CH4/SDIO_D5/I2C1_SDA/CAN1_TX140PE0/FSMC_NBL0141PE1/FSMC_NBL1142PDR_ON143VDD144VCAP171VCAP2106U1STM32F407ZGT6Vref1VDD2nTRST3GND4TDI5GND6TMS7GND8TCK9GND10RTCK11GND12TDO13GND14nRESET15GND16NC17GND18NC19GND20J2JTAGV3.3RESETLCD_CS1RS2WR/CLK3RD4RST5D06D17D28D39D410D511D612D713D814D915D1016D1117D1218D1319D1420D1521GND22BL23VDD3.324VDD3.325GND26GND27BL_VDD28MISO29MOSI30T_PEN31MO32T_CS33CLK34TFTLCD1TFT_LCDD0D1D2D3D4D5D6D7D8D9D10D11D12D13D14D15RESETFSMC_NE4FSMC_NWEA6FSMC_NOELCD_BLT_MISOV3.3GNDT_PENT_CS100nFC1GNDV3.3100nFC2VCC5GN
本文标题:信盈达Cortex-M4开发板原理图
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