DDSAD9959应用电路和配置源程序

DDSAD9959应用电路和配置源程序AD9959是一款有四个DDS通道，最高达500MSPS的数字频率合成芯片。常用电路接法：主要程序：#includeconfig.hvoiddelay(void){unsignedinti;for(i=0;i10;i++);}/*****************************************************************************功能描述:加载寄存器，上升延有效*****************************************************************************/voidrun(void){CLR_IOUPDATE;CLR_IOUPDATE;CLR_IOUPDATE;CLR_IOUPDATE;CLR_IOUPDATE;CLR_IOUPDATE;CLR_IOUPDATE;SET_IOUPDATE;SET_IOUPDATE;}/*****************************************************************************函数名:write_a_byte功能描述:通过串口写一个字节，MSBfirst，上升延有效*****************************************************************************/voidwrite_a_byte(uint8w_data){uint8i;for(i=0;i8;i++){if(w_data&0x80){SET_SDIO0;}else{CLR_SDIO0;}w_data=1;SET_DDSSCLK;CLR_DDSSCLK;}}/*****************************************************************************函数名:write_CSR功能描述:写CSR寄存器：*****************************************************************************/voidwrite_CSR(uint8w_data){CLR_SDIO3;CLR_DDSCS;write_a_byte(0x00);//writeaddress0.CSR'saddressis0.write_a_byte(w_data);SET_DDSCS;SET_SDIO3;}voidwrite_FR1(uint8w_data1,uint8w_data2,uint8w_data3){CLR_SDIO3;CLR_DDSCS;write_a_byte(0x01);//writeaddress1.FR1'saddressis0x01write_a_byte(w_data1);write_a_byte(w_data2);write_a_byte(w_data3);SET_DDSCS;SET_SDIO3;}voidwrite_FR2(uint8w_data1,uint8w_data2){CLR_SDIO3;CLR_DDSCS;write_a_byte(0x02);//writeaddress2write_a_byte(w_data1);write_a_byte(w_data2);SET_DDSCS;SET_SDIO3;}voidwrite_CFR(uint8w_data1,uint8w_data2,uint8w_data3){CLR_SDIO3;CLR_DDSCS;write_a_byte(0x03);write_a_byte(w_data1);write_a_byte(w_data2);write_a_byte(w_data3);SET_DDSCS;SET_SDIO3;}voidwrite_CTW0(uint32F_word)//ChannelFrequencyTuningWord(CTW0){CLR_SDIO3;CLR_DDSCS;write_a_byte(0x04);write_a_byte(((unsignedchar*)(&F_word))[3]);write_a_byte(((unsignedchar*)(&F_word))[2]);write_a_byte(((unsignedchar*)(&F_word))[1]);write_a_byte(((unsignedchar*)(&F_word))[0]);SET_DDSCS;SET_SDIO3;}voidwrite_CPW0(uint16P_word)//ChannelPhase1OffsetWord(CPW0)(0x05){CLR_SDIO3;CLR_DDSCS;write_a_byte(0x05);write_a_byte(((unsignedchar*)(&P_word))[1]&0x3F);write_a_byte((((unsignedchar*)(&P_word))[0]));SET_DDSCS;SET_SDIO3;}voidwrite_ACR(uint32A_word){CLR_SDIO3;CLR_DDSCS;write_a_byte(0x06);write_a_byte(((unsignedchar*)(&A_word))[3]);write_a_byte(((unsignedchar*)(&A_word))[2]);write_a_byte(((unsignedchar*)(&A_word))[1]);SET_DDSCS;SET_SDIO3;}voidwrite_LSR(uint8rising,uint8falling){CLR_SDIO3;CLR_DDSCS;write_a_byte(0x07);write_a_byte(rising);write_a_byte(falling);SET_DDSCS;SET_SDIO3;}voidwrite_RDW(uint32rising){CLR_SDIO3;CLR_DDSCS;write_a_byte(0x08);write_a_byte(((unsignedchar*)(&rising))[3]);write_a_byte(((unsignedchar*)(&rising))[2]);write_a_byte(((unsignedchar*)(&rising))[1]);write_a_byte(((unsignedchar*)(&rising))[0]);SET_DDSCS;SET_SDIO3;}voidwrite_FDW(uint32falling){CLR_SDIO3;CLR_DDSCS;write_a_byte(0x09);write_a_byte(((unsignedchar*)(&falling))[3]);write_a_byte(((unsignedchar*)(&falling))[2]);write_a_byte(((unsignedchar*)(&falling))[1]);write_a_byte(((unsignedchar*)(&falling))[0]);SET_DDSCS;SET_SDIO3;}voidwrite_CTWn(uint8n,uint32w_data){CLR_SDIO3;CLR_DDSCS;write_a_byte(n+0x09);//CTWn'saddressisn+0x09.n=1andn=15.write_a_byte(((unsignedchar*)(&w_data))[3]);write_a_byte(((unsignedchar*)(&w_data))[2]);write_a_byte(((unsignedchar*)(&w_data))[1]);write_a_byte(((unsignedchar*)(&w_data))[0]);SET_DDSCS;SET_SDIO3;}#definePLL_DIV5#definesystemp_frequency(22.1184*1000000*PLL_DIV)voidset_frequency(uint32f){unsignedlonginttemp;temp=(unsignedlongint)f*(0xFFFFFFFF/(float)systemp_frequency+1.0/systemp_frequency);write_CTW0(temp);}uint32change(uint32f){unsignedlonginttemp;temp=(unsignedlongint)f*(0xFFFFFFFF/(float)systemp_frequency+1.0/systemp_frequency);returntemp;}voidAD9959_init(void){uint16i;DDS_DDR=0xff;CLR_DDSRESET;for(i=0;i10000;i++);SET_DDSCS;CLR_DDSSCLK;SET_SDIO3;SET_DDSRESET;for(i=0;i10000;i++);CLR_DDSRESET;for(i=0;i100;i++);}0引言AD9959可以对由于模拟处理(例如滤波、放大)或者PCB布线失配而产生的外部信号通道的不均衡进行有效的校正，从而使系统工程师用相当少的时间和精力去处理这个通常很复杂的系统设计问题。查看最新IC现货74LVTH574MTCXIX0689CE=STK7358A2601-300ERTC62621AXC4002APQ100200AFC6-N供应泰科/(CORCOM)滤波器T2513NH1MBI400S12006035A101JAT2AHLMP-23001AD9959的主要特点AD9959的内部结构如图1所示，主要特性如下：◇有4路带10位DAC的DDS通道，最高取样频率为500MSPS；◇大于65dB的通道隔离度；◇32位频率分辨率；◇14位相位失调分辨率；◇10位输出幅度可缩放的分辨率；◇具有增强数据吞吐量的串行I／O口(SPI)；◇可软件／硬件控制以降低功耗；◇双电源(DDS核1.8V，串行I／O3.3V)；◇内置多器件同步功能；◇内置时钟倍频锁相环(4～20倍倍频)。2AD9959的引脚功能AD9959采用56脚LFCSP封装，各引脚的功能定义如下：SYNC_IN：输入引脚，可同步多片AD9959的SYNC_OUT相连；SYNC_OUT：输出引脚，可同步多片AD9959的SYNC_IN相连；MASTER_RESET：复位输入引脚，高有效；PWR_DWN_CTL：外部电源掉电控制引脚；AGND：模拟地；DVDD：数字电源(1.8V)；DGND：数字地；DAC_RSET：输入引脚，可为DAC设置参考电流，使用时应通过一个1.91kΩ电阻接地；REF_CLK和REF_CLK：参考时钟或振荡输入端(互补输入)，如果使用单端输入方式，则应从REF_CLK引脚连接一个0.1μF的解耦电容到AVDD或AGND；CLK_MODE_SEL：振荡器部分控制引脚，接高电平时，电压不要超过1.8V，接低电平时，振荡器被旁路；LOOP_FILTER：输入端，使用时应串联一个零电阻和680pF电容至最近的AVDD脚(PIN28)；I／O_UPDATE：输入引脚，通过该脚的上升沿可把串行口缓存的数据内容送至激活的寄存器中，I／O_UPDATE信号应与SYNC_CLK信号保持同步，并须满足建立时间与保持时间的要求；CS：片选串口使能信号端，低有效；DVDD_I／O：3.3V数字电源；SYNC_CLK：时钟输出，为内部时钟的1／4，用于同步I／O_UPDATE信号；SCLK：I／O串行操作时钟输入端，在该端的上升沿写入数据，下降沿读出数据；SDIO_0：双向引脚，用于串行操作的数据输入