基于FPGA的图像处理系统

中南民族大学硕士学位论文基于FPGA的图像处理系统姓名：程浏申请学位级别：硕士专业：计算机应用指导教师：汪红2011-05-03IFPGA()FPGAFPGAI2CFIFO()DDRFPGACCDTVP5150PBSA/DITU-RBT.656FIFODDRSDRAMD/ASAA7121HFPGASimulinkSystemGeneratorFPGADSP()FPGAI2CFIFOFPGAIIAbstractDigitalimageprocessingtechnologyhaveawiderangeofapplicationsindailylife,production,construction,nationaldefenseandsecurity.Traditionalimageprocessingtechniquesisdifficulttomeetthetreatmenteffectandreal-timerequirementswhendealingwithlargeamountsofdata.Withtherapiddevelopmentofchiptechnology,makingthehardwaretoachievereal-timedigitalimageprocessingpossible,FPGAisanidealchoiceforreal-timeimageprocessingbecauseofitsparallelcomputingcharacteristics.Thispaperoutlinesthecurrentsituationofdigitalimageprocessing,FPGA'sstructuralfeatures,workingprinciple,developmentprocessesandtools.Afterdepthanalysisofdigitalvideostandards,idiscussthedevelopmentprocessandkeytechnologiesofFPGA-basedreal-timeimageprocessingsystem.Systemrealizesthefunctionofvideocapture,imageprocessingandimagedisplay,includingvideocapturemodule,configurationmodulebasedonI2Cbus,asynchronousFIFOmodule,decodingmodule,DDRcontrollermodule,imageprocessingmoduleanddisplaymodule,allthesefunctionmodulesareimplementinFPGA.ThevideosignalcollectedbyaCCDsensorandtransmittedtothedecoderchipTVP5150PBS,theA/DoperationconvertedthevideosignaltoITU-RBT.656format,theasynchronousFIFObufferthevideodataandthensendtothedecodingmodule,thismoduleconvertedthecolorimagetothegrayimage.TheDDRSDRAMbuffertheimagesframe,thensendimagesignalstotheimageprocessingmodule,imagesignalbeprocessedandthenconvertedtoanalogsignalbytheD/AconverterchipSAA7121H,analogsignaloutputtodisplay.Intheimageprocessingmodule,makefulluseofparallelcomputingfeaturesofFPGA,improvedfilteringalgorithm,combinewithpipelinestructuretoimprovetheprocessingspeedofthealgorithm.Atthesametime,useSimulinkandSystemGeneratortodesignthealgorithmmodular,thesetoolssimplifiestheimplementationprocess,greatlyimproveddevelopmentspeed.Throughthesimulationandtestingtoverifythatthealgorithmcaneffectivelyachievethedesiredfunctions.IIIThedesignshowsthat,FPGAchipscannotonlybeusedasgluelogicfunctions,controlandconnectperipheralmodules,butalsocanreplacetheDSPprocessortoachieveimageprocessingalgorithm.UseFPGAtoimplementimageprocessingisastable,effectiveandeconomicalsolution.KeyWords:FPGA,Imageprocessing,I2CBus,asyncFIFO,Filter1______211.1[1]XDSPCPLD/FPGA/LSI/VLSIDSPFPGADSPFPGA[2]FPGA1.2FPGA2[3](1)(2)(3)(4)(5)(6)RobertSobelLaplaceKirschCanny(7)(8)(9)(10)3(11)(12)[4](1)CPUGPUC/C++JavaCPUGPUCPUGPUCPU(2)ASIC()ASICASICASIC(3)DSP()DSP[5]DSPFPGA4DSPDSP(4)FPGA()FPGA20[6]FPGASRAMFPGAFPGA6I/ORAMFPGAFPGADSP100MHzMACFPGAFPGA1.3(1)FPGAFPGAFPGA(2)(3)(4)(5)(6)5FPGAFPGAPALGALEPLDCPLDFPGAPCBFPGA2.1FPGA4[7](1)PROM()EEPROM()EPROM()3(2)PLDPAL()GAL()PLDPLD(3)XilinxFPGAAlteraPALCPLDPLD(4)SOPC(SystemOnProgrammableChip)SOC(SystemOnChip)SOPCASICFPGA(1)FPGA6(2)SRAM()SRAM(3)PROMPROMPROMEPROMEEPROM(4)FlashFPGAFlashFlashPROMSRAMFPGAFPGA2.2FPGA2.2.1FPGAFPGA(Look-Up-Table)LUTLUTRAM4LUT4161RAMEDARAMLUTLUTFPGALUTLUTLUTFPGA2.2.2FPGAFPGARAMRAMFPGA7(1)PROMFlash(2)PROMFPGA(3)PROMFPGA(4)FPGA2.2.3FPGAFPGA6(CLB)/(IOB)(DCM)RAM2.2.12.2.1FPGA(1)(CLB)CLBFPGACLBCLBRAMROMXilinxSlice4/62.2.2(2)/(IOB)//FPGAI/OEDAFPGA8I/O2.2.2CLB(3)(DCM)(4)RAM(BRAM)BRAMRAMRAMFIFO(5)FPGA(6)DLLPLLDSPCPUFPGAFPGA(7)FPGAASICGBits2.3FPGAFPGAEDAEDAFPGA[8]FPGA2.3.192.3.1FPGA(1)FPGA(2)HDLHDL(3)(4)(5)(6)FPGAFPGAFPGA10(7)(8)(9)FPGAFPGAFPGAFPGA2.4FPGA2.4.1FPGAFPGAXilinx1984XC330XC4000Spartan-3/3A/3EVirtexXilinxFPGAVirtexXilinxVirtex-420500MHz(ASMBL)(LXSXFX)[9](1)500MHz.(2)90nm20(3)I/OChipSync1Gb/sI/O(4)FIFOSmartRAM(5)DCMPMCD(6)XtremeDSPSlice256GMAC/sVirtex-42.4.1112.4.1Virtex-4FPGAVirtex-4SX25SX25SX500MHzDSPRAM128XtremeDSP64GMAC/sDSP2.4.2EDAEDAXilinxHDLI/OISEFoundationFPGA/CPLDISE[10][11]FPGA(1)ISEHDLISEECSIPCoreGeneratorStateCADConstraintEditor(2)XilinxXSTMentorGraphicLeonardoSpectrumSynplicitySynplify(3)ISEHDLBencherMentorGraphicModelSim(4)FPGA12(5)BitGenIMPACTBitFPGAFPGADSPCMATLABHDLXilinxFPGASystemGeneratorSystemGeneratorMathWorksSimulinkMATLAB/SimulinkHDLISESystemGeneratorDSPDSPISESystemGeneratorMATLAB/Simulink2.5FPGAFPGAFPGA133.13.1.13.1.1(CCD)CCDCCDPAL/NTSCTVP5150PBSPAL/NTSC(YUV4:2:2)ITU-RBT.601ITU-RBT.656I2CFPGAI2CBT.656720X576FPGABRAMHYB25D256160BT16M32DDRSDRAMFPGADDRSDRAM3.1.23.1.2FPGAFPGAI2CFIFODDRSDRAMCCDFPGA14TVP5150PBSA/DSAA7121H3.2ITU-RBT.6563.2.1CCD[12]NTSCPALSECAM(1)PAL25HZNTSC30HZ(2)576(3)YUVA/DYUVYUV1994CCIR601ITU-RBT.6013.2.1ITU-RBT.601[13]153.2.1ITU-RBT.601PAL(625/50)NTSC(525/60)()YUVYIQ864858432429CbCrY13.5MHz6.74MHz8bit(PCM)720360720X576720X480360X576360X480(R)216Mbit/s27MB/s2201623224ITU-RBT.60113.5MHz6.75MHz8bit(PCM)PALY864Y720432UV360YUV4:2:2YUV4:2:24:2:2YUV4:4:4YUV4:2:0YUV4:1:13.2.2ITU-RBT.656ITU-RBT.601ITU-RBT.656ITU-RBT.601A4:2:2YCbCr[14]BT.601BT.656BT.601BT.6564:2:2YUV62523-311336-6243.2.1FPGA163.2.12884(EAV)280(SAV)4EAVSAV4FF0000XY34XYXYbit3.2.23.2.2EAV/SAVXYbitbit71bit6Fbit5Vbit4Hbit3P3=VXORHbit2P2=FXORHbit1P1=FXORVbit0P0=FXORVXORH1F10V01H0SAV1EAVP0P1P2P3FVH4bit2bit1440CbYCrYCbYCrY……C