静态存储器IP设计

SanJoseStateUniversitySRAM1SRAMIPforDSP/SoCProjectsBy:IrinaVazirPrabhjotS.BalagganSumandeepKaurCailanShenProjectAdvisor:Dr.DavidParentSanJoseStateUniversitySRAM2TableofContents1.Titlepage………………………………………………………………….12.Tableofcontents………………………………………………………….23.TechnicalSpecifications……………………………………………….….34.SRAMDescription…………………………………………………..…....55.Design……………………………………………………………………..7a.staticRAMcell………………………………………...………………..8b.prechargecircuit……………………………………………………….11c.Senseamplifiers...………...…………….……………………………...13d.muxdesign……………………………………………………………16e.Onewriteandreadcell………………………………………………..20f.Onecolumn……………………..……………………...……………...24g.Decoder…………………...…………………………………………..27h.SRAMsystem…………………………………………………………376.TestandResults………………………………………………………...427.References………………………………………………………….........50SanJoseStateUniversitySRAM3TechnicalSpecifications:FeaturesØOrganization:8-bitX8-bitSRAMICØStorageCapacity:64bitsØ40PinDIPPackage:Figure1Ø5VSupplyØTTLCompatibleLogicPinsØOnchipfrequency:20MHzØSRAMimplementedusingthefullCMOS6-TconfigurationØOperatingTemperature:270CØFabricationTechnology:AMI06(0.6umprocess)Figure1:40PinDIPPackageSanJoseStateUniversitySRAM4PinAssignmentsPin#PinNameDescription1NCNoConnect2NCNoConnect3NCNoConnect4NCNoConnect5NCNoConnect6NCNoConnect7NCNoConnect8NCNoConnect9NCNoConnect10A2DecoderAddressbit(MSB)11A1DecoderAddressbit12A0DecoderAddressbit(LSB)13D0DataIn/Out(LSBofabyte)14D1DataIn/Out15D2DataIn/Out16GNDGround17NCNoConnect18NCNoConnect19NCNoConnect20NCNoConnect21NCNoConnect22NCNoConnect23NCNoConnect24CLKClockEnable25D3DataIn/Out26D4DataIn/Out27D5DataIn/Out28D6DataIn/Out29D7DataIn/Out(MSBofabyte)30CSChipSelect31NCNoConnect32REReadEnable33NCNoConnect34NCNoConnect35NCNoConnect36NCNoConnect37WEWriteEnable38NCNoConnect39NCNoConnect40VDDPower+5VTable1:PinassignmentsSanJoseStateUniversitySRAM5SRAMDescription:8-bitX8-bitSRAMICwasdesignedforfutureDSP/SoCapplications.TheSRAMICisR/Wmemorycircuitthatpermitsthemodification(writing)ofdatabitstobestoredinamemoryarray,aswellastheirretrieval(reading).TheSRAMICwasdevelopedusingtheCDSIC446,cadenceICdesignenvironment.ThedesignwasbasedontheAMI0.6-micronprocess.TheSRAMICdesignconsistsofSRAMcells,precharge,senseamplifiers,mux,NANDgates,ANDgates,NORgatesandrowdecoder.Themostimportantpartisthecellasalltheothercircuitryisconnectedtoandaroundthecell.Thepopular,fullCMOS6-transistorcellconfigurationwasusedtodesigntheSRAMmemoryarray.ThefullCMOSconfigurationisshowninfigure2.SomeoftheadvantagesofusingfullCMOSSRAMconfigurationarelowstaticpowerdissipation,superiornoisemargins,highswitchingspeedsandsuitabilityforhigh-densitySRAMarrays(2).Inordertodesigna64bitSRAM,64fullCMOS6-Tcellswereused.EachfullCMOS6-Tcellhasacapabilityofstoring1bit.SanJoseStateUniversitySRAM6Figure2:6-TcellconfigurationTheSRAMICwastestedontheSRAMverificationboardwhichisasimpleput-inandtake-outtester.Theonboardfrequencyoftheverificationboardis14MHz.Thepre-writtentestprogramthatisstoredintheEEPROMteststheSRAMICandshowserrormessageswitharedLEDand7-segmentdisplay.SanJoseStateUniversitySRAM7Design:SanJoseStateUniversitySRAM8StaticRAMCellThefullCMOS6-transistorcellconfigurationwaschosenforthecellarray.Figure3showstheschematicofthe6-Tcell.The6-Tcellconsistsoftwocrosscoupledinvertersconnectedwiththetwonmostransistorsonboththeends.Eachnmostransistorisconnectedtoaninverterononesideandbitlineontheotherside.ThedatavalueisstoredinthenetconnectedtotheleftsideoftheN3nmosinfigure3.TheinversedatavalueisstoredinthenetconnectedtotherightsideoftheN0nmosinfigure3.TheinputsignalA0inthefigure3comesfromtherowdecoder,allowsthecelltobeconnectedtothecomplementarybitlinesduringreadingandwritinganddisconnectsotherwise.Figure3:Schematicof6-TcellTodeterminethesizesofthetransistorsofthecell,simpleW/Lratiosshowninequation1andequation2wereused(1).IntheequationsthesubscriptsshowtheSanJoseStateUniversitySRAM9transistornumberfromfigure3.Equation1showsasimplerelationbetweentwonmosN3andN1.Equation2showsasimplerelationbetweenpmosandnmosP5andN3.Usingthetwoequations,approximatevaluesofthewidthsofthetransistorwerecalculatedandthedesignwassimulated.Thefinalwnandwpvaluesareshowninfigure3.Figure4showsthelayoutoftheSRAMcell.OneofthemajorconsiderationsforlayoutofthecellwasthetypeofmetalusedforVDD,addresslinesandground.Infigure4,thethreehorizontalparallelmetal2linesareVDD,addresslineandgroundrespectively.Thetwoverticalparallelmetal1linesarethetwobitlines.Generally,metal1isusedforVDDandground.Forthelayoutofcellmetal2wasusedforlayingVDD,addresslinesandgroundbecausebyusingmetal2theviacapacitanceswerereducedastheinvertersinthecellarecross-coupledanditenablestheconnectionofthepmosandthenmosusingmetal1.SanJoseStateUniversitySRAM10Figure4:Layoutof6-TcellSanJoseStateUniversitySRAM11PrechargecircuitThefunctionoftheprechargecircuitistochargethebit-lineandinversebit-lines(bit-linebar)to5V.Theprechargeenablesthebit-linestobechargedhighatalltimesexceptduringwriteandreadcycle.Figure5showstheschematicofthepre-chargecircuit.Thepmostransistorsusedfortheprechargecircuitare1.5µmeach,