3D-IC-TSV-介绍与工艺流程

Chapter7Introductionto3DIntegrationTechnologyusingTSVJin-FuLiDepartmentofElectricalEngineeringNationalCentralUniversityJungli,TaiwanAdvancedReliableSystems(ARES)Lab.Jin-FuLi,EE,NCU2Why3DIntegrationAnExemplaryTSVProcessFlowStackingStrategiesConceptof3DICDesignSummaryOutlineAdvancedReliableSystems(ARES)Lab.Jin-FuLi,EE,NCUICTechnologyEvolutionChipSingle-chippackagePrintedwiringboard(PCB)3D-SIP3D-ICEnergy/PowerProcessorMemoryStackRFADCDACNanoDeviceMEMSOtherSensors,ImagersChemical&BioSensorsAdvancedReliableSystems(ARES)Lab.Jin-FuLi,EE,NCU4Why3DIntegrationIntegratingmoreandmoretransistorsinasinglechiptosupportmoreandmorepowerfulfunctionalityisatrendUsing2DintegrationtechnologytoimplementsuchcomplexchipsismoreandmoreexpensiveanddifficultSomealternativetechnologiesattemptingtocopewiththebottlenecksof2Dintegrationtechnologyhavebeenproposed3Dintegrationtechnologyusingthroughsiliconvia(TSV)hasbeenacknowledgedasoneofthefuturechipdesigntechnologiesAdvancedReliableSystems(ARES)Lab.Jin-FuLi,EE,NCU53DIntegrationTechnologyUsingTSV3DintegrationtechnologyusingTSVMultiplediesarestackedandTSVisusedfortheinter-dieinterconnectionThefabricationflowofa3DICDie/waferpreparationDie/waferassemblyDie1Die2Die3TSVAdvancedReliableSystems(ARES)Lab.Jin-FuLi,EE,NCU6WhatisTSVThroughSiliconVia(TSV):AviathatgoesthroughthesiliconsubstrateUsedfordiesstackingTypicalTSVtechnologiesVia-first,via-middle,andvia-lasttechnologiesCMOSTopBumpTopBumpSiO2insulatorViamadebylaserDiameterAlwiringTSVWiringlayer50umorlessAdvancedReliableSystems(ARES)Lab.Jin-FuLi,EE,NCU7Via-FirstTSVVia-FirstTSVTechnologySource:Yole,2007.(1)BeforeCMOS(2)AfterCMOS&BEOLAdvancedReliableSystems(ARES)Lab.Jin-FuLi,EE,NCU8Via-LastTSVVia-LastTSVTechnologySource:Yole,2007.(1)AfterBEOL&beforebonding(2)AfterbondingStep1:AwaferwithCMOScircuitsAdvancedReliableSystems(ARES)Lab.Jin-FuLi,EE,NCU9AnExemplaryVia-LastProcessFlow(1/6)……MOSFET…MOSFETSubstrateRef：ITRIStep2:viaetchingAdvancedReliableSystems(ARES)Lab.Jin-FuLi,EE,NCU10AnExemplaryVia-LastProcessFlow(2/6)……MOSFET…MOSFETSubstrateViamachining(byetchingorlaserdilling)Ref：ITRIStep3:viafillingAdvancedReliableSystems(ARES)Lab.Jin-FuLi,EE,NCU11AnExemplaryVia-LastProcessFlow(3/6)……MOSFET…MOSFETSubstrateViafillingRef：ITRIStep4:waferthinningAdvancedReliableSystems(ARES)Lab.Jin-FuLi,EE,NCU12AnExemplaryVia-LastProcessFlow(4/6)………Waferthinning50~100μmRef：ITRIStep5:microbumpformingAdvancedReliableSystems(ARES)Lab.Jin-FuLi,EE,NCU13AnExemplaryVia-LastProcessFlow(5/6)………MicroBumpRef：ITRIStep6:stackingAdvancedReliableSystems(ARES)Lab.Jin-FuLi,EE,NCU14AnExemplaryVia-LastProcessFlow(6/6)TSVMicro(μ)BumpABF(AjinomotoBuilt-inFilm)………………Ref：ITRIAdvancedReliableSystems(ARES)Lab.Jin-FuLi,EE,NCU15AnExemplary3DICusingVia-LastTSVNWellNWellNWellP-Substrate2ndChipTSVN+N+N+N+N+N+N+P+P+P+P+P+NWellNWellNWellP-Substrate1stChipTSVN+N+N+N+N+N+N+P+P+P+P+P+P-Substrate3rdChipBondingAdhesiveBondingAdhesiveAdvancedReliableSystems(ARES)Lab.Jin-FuLi,EE,NCU163-Tier3DICCross-SectionSource:E.G.Friedman,UniversityofRochester.AdvancedReliableSystems(ARES)Lab.Jin-FuLi,EE,NCU17Die/WaferAssemblyBondingtechnologiesfor3DICsWafer-to-wafer(W2W),Die-to-Wafer(D2W),andDie-to-Die(D2D)ComparisonofdifferentbondingtechnologiesD2DD2WW2WYieldFlexibilityProductionThroughputHighHighLowHighGoodGoodLowPoorHighAdvancedReliableSystems(ARES)Lab.Jin-FuLi,EE,NCU18StackingStrategiesLewis,D.L.etal,“AScanIslandBasedDesignEnablingPrebondTestabilityinDieStackedMicroprocessors,”inproc.IEEEInternationalTestConference(ITC),2007,pp.1-8MetalActiveSiBulkSiD2DViasDie2Die1μBumpTSVface-to-faceback-to-backface-to-backμBumpμBumpAdvancedReliableSystems(ARES)Lab.Jin-FuLi,EE,NCU19FabricationStepsforFace-to-FaceStackingMetalActiveSiBulkSiDie1Die2Die1MetalActiveSiBulkSiDie1Die2MetalActiveSiBulkSiDie2MetalActiveSiBulkSiDie1Die2MetalActiveSiBulkSiDie1Die21122334455Loh,GabrielH.etal,“ProcessorDesignin3DDie-StackingTechnologies,”inIEEEMicro,vol.27,issue3,pp.31-48,2007AdvancedReliableSystems(ARES)Lab.Jin-FuLi,EE,NCU20FabricationStepsforFace-to-BackStackingMetalActiveSiBulkSiDie1Die2MetalActiveSiBulkSiDie1Die2MetalActiveSiBulkSiDie1Die2MetalActiveSiBulkSiDie1Die2MetalActiveSiBulkSiDie1Die21122334455HandlewaferLoh,GabrielH.etal,“ProcessorDesignin3DDie-StackingTechnologies,”inIEEEMicro,vol.27,issue3,pp.31-48,2007AdvancedReliableSystems(ARES)Lab.Jin-FuLi,EE,NCU21ElectricalCharacteristicsofTSVCapacitanceofTSVCMOSTopBumpDiameterAlwiringTSVWiringlayerTSVLengthDielectricThicknessTSVDia[um]TSVDielThk[nm]TSVLength[um]Cap[fF]55020239.5510020135.2105020496.41010020288.3Source:ProceedingsofIEEE,pp.101,Jan.2009AdvancedReliableSystems(ARES)Lab.Jin-FuLi,EE,NCU22RCCharacteristicsofTSV……Die1Die2MOSFETM1M2M9via9via1via2RCviastack~0.35*RCviastackD2Dvia1-mmtop-levelmetal4xminimumsizeF2FD2Dvia1FO4=22ps(BSIM70nm)225ps11FO48ps~1/3*FO4Loh,GabrielH.etal,“ProcessorDesignin3DDie-StackingTechnologies,”inIEEEMicro,vol.27,issue3,pp.31-48,2007AdvancedReliableSystems(ARES)Lab.Jin-FuLi,EE,NCU23Benefitsof3Dintegrationover2DintegrationHigh