DE1-SoC

5544332211DDCCBBAAALTERACycloneVSoCDevelopment&EducationBoard(DE1-SoC)CONTENT1CoverPagePAGEPAGECONTENT234567891011121314BlockDiagramFPGABANK3,BANK4FPGABANK5,BANK6FPGABANK7,BANK8FPGAClocks,GNDFPGAConfigurationFPGADecouplingFPGAPowerUSBBlasterIIJTAGChainGPIO0GPIO1SDRAM,HPSQSPIFlashHPSDDR3SDRAM15161718192021222324252627282930ADV7123VGAADV7180VideoDecoderAudioCODEC7-SegmentDisplay,LEDFPGABUTTON,SwitchADC,PS2,IRTx,IRRx2-portUSBHost1GagabitEthernetUARTtoUSB,SDCARDAccelerometer,LTCConnectorI2CMultiplexer,HPSBUTTON,HPSLEDPower-1.1VPower-5V,3.3VPower-9V,2.5V,1.5VPower-1.2V,1.8V,DDR3VREF,DDR3VTTTitleSizeDocumentNumberRevDate:SheetofCopyright(c)2013byTerasicTechnologiesInc.Taiwan.Nopartofthisschematicdesignmaybereproduced,duplicated,orusedwithoutthepriorwrittenpermissionofTerasic.Allrightsreserved.CoverPageBDE1-SoCBoardB130Monday,November25,2013TitleSizeDocumentNumberRevDate:SheetofCopyright(c)2013byTerasicTechnologiesInc.Taiwan.Nopartofthisschematicdesignmaybereproduced,duplicated,orusedwithoutthepriorwrittenpermissionofTerasic.Allrightsreserved.CoverPageBDE1-SoCBoardB130Monday,November25,2013TitleSizeDocumentNumberRevDate:SheetofCopyright(c)2013byTerasicTechnologiesInc.Taiwan.Nopartofthisschematicdesignmaybereproduced,duplicated,orusedwithoutthepriorwrittenpermissionofTerasic.Allrightsreserved.CoverPageBDE1-SoCBoardB130Monday,November25,20135544332211DDCCBBAATitleSizeDocumentNumberRevDate:SheetofCopyright(c)2013byTerasicTechnologiesInc.Taiwan.Nopartofthisschematicdesignmaybereproduced,duplicated,orusedwithoutthepriorwrittenpermissionofTerasic.Allrightsreserved.BlockDiagramBDE1-SoCBoardB230Wednesday,February12,2014TitleSizeDocumentNumberRevDate:SheetofCopyright(c)2013byTerasicTechnologiesInc.Taiwan.Nopartofthisschematicdesignmaybereproduced,duplicated,orusedwithoutthepriorwrittenpermissionofTerasic.Allrightsreserved.BlockDiagramBDE1-SoCBoardB230Wednesday,February12,2014TitleSizeDocumentNumberRevDate:SheetofCopyright(c)2013byTerasicTechnologiesInc.Taiwan.Nopartofthisschematicdesignmaybereproduced,duplicated,orusedwithoutthepriorwrittenpermissionofTerasic.Allrightsreserved.BlockDiagramBDE1-SoCBoardB230Wednesday,February12,20145544332211DDCCBBAAVCCIO=3.3VVCCIO=3.3VUSB_B2_DATA1USB_B2_DATA2USB_B2_DATA3USB_B2_DATA4USB_B2_DATA6USB_B2_DATA7GPIO_012GPIO_015GPIO_018GPIO_032LEDR0LEDR1GPIO_013GPIO_014GPIO_09GPIO_04GPIO_031GPIO_022GPIO_011GPIO_010GPIO_034GPIO_020GPIO_08GPIO_05LEDR2LEDR4GPIO_07GPIO_06GPIO_021GPIO_035GPIO_030GPIO_033GPIO_123GPIO_111GPIO_129GPIO_128GPIO_026GPIO_027GPIO_01GPIO_016GPIO_023GPIO_126GPIO_028GPIO_029GPIO_03GPIO_017GPIO_124GPIO_122GPIO_121GPIO_120GPIO_131GPIO_130GPIO_019GPIO_024GPIO_117GPIO_118GPIO_19GPIO_119GPIO_132GPIO_15LEDR3LEDR5GPIO_113GPIO_116GPIO_115GPIO_114GPIO_025GPIO_133LEDR6GPIO_134GPIO_110GPIO_112GPIO_17GPIO_18GPIO_135GPIO_13GPIO_11GPIO_12GPIO_125GPIO_127GPIO_14GPIO_16SW0SW1SW2SW5DRAM_ADDR10DRAM_ADDR12DRAM_ADDR0DRAM_DQ0DRAM_DQ2DRAM_DQ3DRAM_DQ12DRAM_DQ4DRAM_DQ9DRAM_DQ6DRAM_DQ7DRAM_DQ8DRAM_DQ5DRAM_DQ10DRAM_DQ11DRAM_DQ1DRAM_DQ13DRAM_DQ14DRAM_DQ15DRAM_ADDR6DRAM_ADDR4DRAM_ADDR8DRAM_ADDR1DRAM_ADDR11DRAM_ADDR9DRAM_ADDR2DRAM_ADDR3DRAM_ADDR5KEY1KEY0DRAM_DQ[15..0]14KEY[3..0]6,20DRAM_ADDR[12..0]6,14USB_SDA10USB_B2_DATA[7..0]7,10USB_B2_CLK10USB_RESET_n10USB_EMPTY10USB_FULL10USB_WR_n10USB_RD_n10USB_OE_n10USB_SCL10GPIO_0[35..0]6,12GPIO_1[35..0]6,13SW[9..0]7,20LEDR[9..0]4,19FAN_CTRL7DRAM_CAS_N14DRAM_CS_N14DRAM_RAS_N14DRAM_BA014DRAM_UDQM14DRAM_CKE14DRAM_WE_N14DRAM_LDQM14ADC_SCLK21ADC_DOUT21ADC_DIN21ADC_CS_N21TitleSizeDocumentNumberRevDate:SheetofCopyright(c)2013byTerasicTechnologiesInc.Taiwan.Nopartofthisschematicdesignmaybereproduced,duplicated,orusedwithoutthepriorwrittenpermissionofTerasic.Allrightsreserved.FPGABANK3,BANK4BDE1-SoCBoardB330Monday,November25,2013TitleSizeDocumentNumberRevDate:SheetofCopyright(c)2013byTerasicTechnologiesInc.Taiwan.Nopartofthisschematicdesignmaybereproduced,duplicated,orusedwithoutthepriorwrittenpermissionofTerasic.Allrightsreserved.FPGABANK3,BANK4BDE1-SoCBoardB330Monday,November25,2013TitleSizeDocumentNumberRevDate:SheetofCopyright(c)2013byTerasicTechnologiesInc.Taiwan.Nopartofthisschematicdesignmaybereproduced,duplicated,orusedwithoutthepriorwrittenpermissionofTerasic.Allrightsreserved.FPGABANK3,BANK4BDE1-SoCBoardB330Monday,November25,2013Bank4A5CSEMA5F31U20-10IO_4A/RZQ_0/DIFFIO_TX_B41NAG17IO_4A/DIFFIO_RX_B42N/DQ6B/B_DQ_0AF18IO_4A/DIFFIO_TX_B41P/DQ6B/B_DQ_2AG16IO_4A/DIFFIO_RX_B42P/DQ6B/B_DQ_1AE17IO_4A/DIFFIO_RX_B43N/DQSN6B/B_DQSN_0W16IO_4A/DIFFIO_TX_B44N/DQ6B/B_DQ_3AF16IO_4A/DIFFIO_RX_B43P/DQS6B/B_DQS_0V16IO_4A/DIFFIO_TX_B44P/B_ODT_0AE16IO_4A/DIFFIO_TX_B45N/DQ6B/B_ODT_1AK16IO_4A/DIFFIO_RX_B46N/DQ6B/B_DQ_4AH20IO_4A/DIFFIO_TX_B45P/DQ6B/B_DQ_6AJ16IO_4A/DIFFIO_RX_B46P/DQ6B/B_DQ_5AG21IO_4A/DIFFIO_TX_B48N/DQ6B/B_DQ_7AH18IO_4A/DIFFIO_TX_B48P/DQ6B/B_DM_0AH17IO_4A/DIFFIO_TX_B49N/GNDAH19IO_4A/DIFFIO_RX_B50N/DQ7B/B_DQ_8AK18IO_4A/DIFFIO_TX_B49P/DQ7B/B_DQ_10AG18IO_4A/DIFFIO_RX_B50P/DQ7B/B_DQ_9AJ17IO_4A/DIFFIO_RX_B51N/DQSN7B/B_DQSN_1W17IO_4A/DIFFIO_TX_B52N/DQ7B/B_DQ_11AK19IO_4A/DIFFIO_RX_B