booth乘法器

Booth乘法器verilog代码（3：2）压缩将每个模块的代码建一个.V文件，然后选中测试文件进行仿真。本程序可仿真成功。Booth编码规则例子测试文件moduletb_booth_mul();regsigned[15:0]multiplicand;regsigned[15:0]multiplier;wire[31:0]product;parameterBITWIDTH=16;regclock,reset;initialbeginreset=0;clock=1'b0;forever#5clock=~clock;endalways@(posedgeclock)begin#5multiplicand=$random($random);multiplier=$random($random);end//instantiationbooth_mulu_booth_mul(.multiplicand(multiplicand),.multiplier(multiplier),.product(product),.clk(clock),.reset(reset));endmodulebooth乘法器主程序文件（不压缩）modulebooth_mul(multiplicand,multiplier,product,clk,reset);parameterBITWIDTH=16;inputclk,reset;input[BITWIDTH-1:0]multiplier;input[BITWIDTH-1:0]multiplicand;output[2*BITWIDTH-1:0]product;reg[2*BITWIDTH-1:0]product;reg[15:0]multiplicand1,multiplier1;wire[8:0]ss;wirea,e0,e1;wires0,s1,s2,s3,s4,s5,s6,s7,s8;wire[2*BITWIDTH-1:0]tmp_prod;wire[BITWIDTH+3:0]tp8;wire[BITWIDTH+5:0]tp1,tp2,tp3,tp4,tp5,tp6,tp7;wire[BITWIDTH+3:0]j0;wire[BITWIDTH+2:0]j1,j2,j3,j4,j5,j6;wire[BITWIDTH+1:0]j7;wire[BITWIDTH:0]j8;assigne0=multiplicand[15];assigne1=multiplier[15];assigna=e0|e1;always@(posedgeclkorposedgeresetornegedgeclk)beginif(reset)product=0;elsebeginif(a)beginif(multiplicand[15])multiplicand1=~multiplicand+1'b1;elsemultiplicand1=multiplicand;if(multiplier[15])multiplier1=~multiplier+1'b1;elsemultiplier1=multiplier;endelse{multiplicand1,multiplier1}={multiplicand,multiplier};endend//partialproductbfj_9j_9(.multiplicand1(multiplicand1),.multiplier1(multiplier1),.s0(s0),.s1(s1),.s2(s2),.s3(s3),.s4(s4),.s5(s5),.s6(s6),.s7(s7),.s8(s8),.j0(j0),.j1(j1),.j2(j2),.j3(j3),.j4(j4),.j5(j5),.j6(j6),.j7(j7),.j8(j8));assigntmp_prod=j0000+{j1000[25:0],6'b000000}+{s7,1'b0,s6,1'b0,s5,1'b0,s4,1'b0,s3,1'b0,s2,1'b0,s1,1'b0,s0};//partialproductaccumulatorassigntp1=j0+{j1,1'b0,s0};assigntmp_prod[1:0]=tp1[1:0];assigntp2=tp1[BITWIDTH+5:2]+{j2,1'b0,s1};assigntmp_prod[3:2]=tp2[1:0];assigntp3=tp2[BITWIDTH+5:2]+{j3,1'b0,s2};assigntmp_prod[5:4]=tp3[1:0];assigntp4=tp3[BITWIDTH+5:2]+{j4,1'b0,s3};assigntmp_prod[7:6]=tp4[1:0];assigntp5=tp4[BITWIDTH+5:2]+{j5,1'b0,s4};assigntmp_prod[9:8]=tp5[1:0];assigntp6=tp5[BITWIDTH+5:2]+{j6,1'b0,s5};assigntmp_prod[11:10]=tp6[1:0];assigntp7=tp6[BITWIDTH+5:2]+{j7,1'b0,s6};assigntmp_prod[13:12]=tp7[1:0];assigntp8=tp7[BITWIDTH+5:2]+{j8[BITWIDTH-1],1'b0,s7};assigntmp_prod[2*BITWIDTH-1:14]=tp8[BITWIDTH+1:0];always@(posedgeclkorposedgeresetorposedgeclk)if(reset)product=0;elseif(e0^e1)product={1'b1,~tmp_prod[2*BITWIDTH-2:0]+1'b1};elseproduct=tmp_prod;endmodulebooth乘法器3：2压缩文件modulebooth_mul(multiplicand,multiplier,product,clk,reset);parameterBITWIDTH=16;inputclk,reset;input[BITWIDTH-1:0]multiplier;input[BITWIDTH-1:0]multiplicand;output[2*BITWIDTH-1:0]product;reg[2*BITWIDTH-1:0]product;reg[15:0]multiplicand1,multiplier1;wire[8:0]ss;wirea,e0,e1;wires0,s1,s2,s3,s4,s5,s6,s7,s8;wire[2*BITWIDTH-1:0]tmp_prod;wire[BITWIDTH+3:0]tp8;wire[BITWIDTH+5:0]tp1,tp2,tp3,tp4,tp5,tp6,tp7;wire[BITWIDTH+3:0]j0;wire[BITWIDTH+2:0]j1,j2,j3,j4,j5,j6;wire[BITWIDTH+1:0]j7;wire[BITWIDTH:0]j8;assigne0=multiplicand[15];assigne1=multiplier[15];assigna=e0|e1;always@(posedgeclkorposedgeresetornegedgeclk)beginif(reset)product=0;elsebeginif(a)beginif(multiplicand[15])multiplicand1=~multiplicand+1'b1;elsemultiplicand1=multiplicand;if(multiplier[15])multiplier1=~multiplier+1'b1;elsemultiplier1=multiplier;endelse{multiplicand1,multiplier1}={multiplicand,multiplier};endend//partialproductbfj_9j_9(.multiplicand1(multiplicand1),.multiplier1(multiplier1),.s0(s0),.s1(s1),.s2(s2),.s3(s3),.s4(s4),.s5(s5),.s6(s6),.s7(s7),.s8(s8),.j0(j0),.j1(j1),.j2(j2),.j3(j3),.j4(j4),.j5(j5),.j6(j6),.j7(j7),.j8(j8));//3:2yasuo1:9-6wire[21:0]j0_s,j1_s;wire[19:0]j0_c,j1_c,j2_s;wire[17:0]j2_c;yasuo1y9_6(.j0(j0),.j1(j1),.j2(j2),.j3(j3),.j4(j4),.j5(j5),.j6(j6),.j7(j7),.j8(j8),.j0_s(j0_s),.j0_c(j0_c),.j1_s(j1_s),.j1_c(j1_c),.j2_s(j2_s),.j2_c(j2_c));//3:2yasuo2:6-4wire[23:0]j00_s,j00_c;wire[22:0]j10_s;wire[19:0]j10_c;yasuo2y6_4(.j00(j0_s),.j01(j0_c),.j10(j1_s),.j11(j1_c),.j20(j2_s),.j21(j2_c),.j00_s(j00_s),.j00_c(j00_c),.j10_s(j10_s),.j10_c(j10_c));//3:2yasuo3:4-3wire[28:0]j20_s;wire[26:0]j20_c;yasuo3y4_3(.j000(j00_s),.j100(j00_c),.j200(j10_s),.j20_s(j20_s),.j20_c(j20_c));//3:2yasuo4:3-2wire[31:0]j0000;wire[26:0]j1000;yasuo4y3_2(.j10(j20_s),.j20(j20_c),.j30(j10_c),.j0000(j0000),.j1000(j1000));assigntmp_prod=j0000+{j1000[25:0],6'b000000}+{s7,1'b0,s6,1'b0,s5,1'b0,s4,1'b0,s3,1'b0,s2,1'b0,s1,1'b0,s0};always@(posedgeclkorposedgeresetorposedgeclk)if(reset)product=0;elseif(e0^e1)product={1'b1,~tmp_prod[2*BITWIDTH-2:0]+1'b1};elseproduct=tmp_prod;endmodule加法器moduleadd3(a,b,c,si,ci);inputa,b,c;outputsi,ci;wiresi,ci;assignsi=a^b^c;assignci=a&b|(a^b)&c;endmodulebooth编码modulebooth_recoder(multiplicand,code,pp,s);parameterBITWIDTH=16;input[BITWIDTH-1:0]multiplicand;input[2:0]code;output[BITWIDTH:0]pp;outputs;reg[BITWIDTH:0]pp;regs;always@(multiplicandorcode)case(code)3'b000:pp={(BITWIDTH+1){1'b0}};//+03'b001:pp={multiplicand[15],multiplicand};//+M3'b010:pp={multiplicand[15],multiplicand}