ISA总线时序图

1ISABusTimingDiagramsSBS’sISAbustimingdiagramsarederivedfromdiagramsintheIEEEP996draftspecificationwhichwere,inturn,derivedfromthetimingoftheoriginalIBMATcomputer.PleasenotethattheIEEEP996draftspecificationwasnevercompletedbytheIEEEandisnotanIEEEapprovedspec.Also,the“latest”IEEEdraftisknowntocontainerrors.IntheabsenceofanapprovedIEEEspecification,manufacturersofPCchipsetsattempttomeeta“consensus”ISAbusstandard.ThishasresultedinminorvariationsinsignalinterpretationandtimingamongthevariousPCchipsetvendors.Forthisreason,SBSrecommendsthatdesignersofinterfacestotheISAbususetheminimumnumberofbussignalsneededtoperformarequiredfunction(e.g.chipselectionorsignalsynchronization).Forexample,atleastonepopularchipsetdoesnotdriveAENhighduringREFRESH.Incertaininstances,SBShasaddedlogictoimprovebustimingand/orsignalrelationshipsonCPUandperipheralboards.SBS’sISAbustimingdiagramsincludeseveralcorrectionsrelativetotheIEEEP996draftspecification.However,sincethesediagramsarederivedfromanuncompletedandunapprovedIEEEspecification,theymaycontainothererrors.ForcomprehensivetechnicaldetailsontheISAarchitectureandbus,SBSrecommendsthefollowingbook:ISA&EISATheoryandOperation,byEdwardSolari;publishedbyAnnabooks().ThisbookcontainsadetailedtechnicalexpositionoftheISAandEISAbusesandiswrittenbytheprincipalauthoroftheIEEEP996draftspecification.ISABusTimingDiagrams2REFTYPESIZEDESCRIPTIONDRIVERRECEIVERMINMAXMINMAX1M,IO8/16LAsetuptoBALEdeasserted1111002M,IO8/16BALEpulsewidth61503M,IO8/16LAholdfromBALEdeasserted26154a4bMM168LAsetuptoMEMx*assertedLAsetuptoMEMx*asserted1201831091725M8/16MEMCS16*validfromLA661026M8/16MEMCS16*holdfromLA007a7b7cMIOM,IO16168SA,SBHE*setuptoMEMx*SA,SBHE*setuptoIOx*SA,SBHE*setuptoIOx*orMEMx*391021022891918a8b8c8dMIOMM,IO1616168CommandwidthCommandwidthCommandwidthwithENDXFR*assertedCommandwidth2401651035412191549253010a10b10c10dMIOM,IOM,IO1616168ReaddataaccessReaddataaccessReaddataaccesswithENDXFR*assertedReaddataaccess173110484821951327050411a11b11c11dMIOM,IOM,IO161688WritedatasetupWritedatasetupWritedatasetup(even)Writedatasetup(odd)-34337-45-4522-4-5612M,IO8/16SA,SBHE*hold534213a13b13cMMIO1688/16CommanddeassertedCommanddeassertedCommanddeasserted1081701709715915915a15bM,IOM,IO8/168/16ReaddataholdWritedatahold02502516M,IO8/16ReadcommandtoSDdisabled303017M16ENDXFR*assertedfromcommand103218IO8/16IOCS16*assertedfromSA7412219IO8/16IOCS16*holdfromSA0020a20bM,IOM,IO8/168IOCHRDYvalidfromcommandassertedIOCHRDYvalidfromcommandasserted7037315946221M,IO8/16IOCHRDYdeassertedpulsewidth125156001251561122M,IO8/16CommandholdfromIOCHRDY12523M,IO8/16BALEassertedfromcommanddeasserted463524M,IO8/16Clockperiod(Tclk)12016712016725a25bM,IOM,IO8/168DatasetuptoIOCHRDYdeasserted(8-biteven)DatasetuptoIOCHRDYdeasserted(8-bitodd)8575746426a26bMM168LAholdtoMEMx*activeLAholdtoMEMx*active41-2130-3228M16ENDXFR*setuptoSYSCLKfallingedge2229M16ENDXFR*holdfromSYSCLKfallingedge2236M16LAsetuptoENDXFR*asserted18015837M16SAsetuptoENDXFR*asserted8361Table1.MemoryandI/OTiming3MEMR*MEMW*SD15..0SA16..071081311161512MEMCS16*Note1IOCHRDYLA23..17BALE2143262356SBHE*SYSCLK24Note1:IOCHRDYtimingsapplyifdeasserted.SeeFigure4.Figure1.16-bitMemoryTimingISABusTimingDiagrams4IOR*,IOW*SD15..0710813111615SA15..0SBHE*181923IOCS16*Note1IOCHRDYBALE12Note1:IOCHRDYtimingsapplyifdeasserted.SeeFigure4.Figure2.16-bitI/OTiming5MEMR*MEMW*SD7..0SA19..071081311161512MEMCS16*Note1IOCHRDYLA23..17BALE2143262356IOR*IOW*Note1:IOCHRDYtimingsapplyifdeasserted.SeeFigure4.Figure3.8-bitMemoryandI/OTimingISABusTimingDiagrams6SD15..0IOCHRDYSMEMR*SMEMW*20222521IOR*IOW*Figure4.IOCHRDYTiming7SYSCLKIOCHRDYENDXFR*SD15..0MEMR*MEMW*LA23..17SA19..0273729283610c8c17Note1:AssertionofENDXFR*withinthemaximumtimefromcommandisonlyrequiredfora16-bitcyclewithzerowaitstates.Otherwise,ENDXFR*maybeassertedatanytimeduringthecyclewhilecommandisasserted.Figure5.ENDXFR*TimingISABusTimingDiagrams8REFDESCRIPTIONDRIVERRECEIVERMINMAXMINMAX1a1bDACKn*,AENsetuptoIOR*DACKn*,AENsetuptoIORW*76321653102AddresssetuptoMEMW*,IOW*102913a3bIOR*setuptoMEMW*MEMR*setuptoIOW*246023404a4b4cDataaccessfromIOR*8/16bitDataaccessfromMEMR*16bitDataaccessfromMEMR*8bit2201733322421953375DatasetuptoIOW*unasserted1641426Readcommandholdfromwritecommand50397SBHE*,addresshold53428Dataholdfromreadcommand1109a9bIOCHRDYdeassertedfrom16bitmemorycommandIOCHRDYdeassertedfrom8bitmemorycommand8138410340610TCholdfromcommandunasserted604911a11bIOR*pulsewidthMEMR*pulsewidth79754778653612IOW*,MEMW*width50048913a13b13cDACKn*holdfromIOW*DACKn*holdfromIOW*AENholdfromcommand114173411031623014DREQinactivefromIOx*11914115IOCHRDYlowwidthTclk15600Tclk1561116TCsetuptocommandunasserted511500Table2.DMATiming9DRQnSA16..0SBHELA23...17IOR*,MEMR*TCIOW*,MEMW*IOCHRDYAENDACKn*131421a117312645891610SD15..015Notes1and4Note21bNote1:DRQnmaybedeassertedanytimeafterDACKn*duringablockmodeDMAtransfer.Note2:IOCHRDYmaybedeassertedtoinsertadditionalwaitstates.Additionalbuswaitstatesareaddedinunitsoftwobusclocks.Note3:TheDMAcontrolleractivatesTCduringt