Verilog的150个经典设计实例

VerilogHDL-1-3.14moduleadder4(cout,sum,ina,inb,cin);output[3:0]sum;outputcout;input[3:0]ina,inb;inputcin;assign{cout,sum}=ina+inb+cin;endmodule3.24modulecount4(out,reset,clk);output[3:0]out;inputreset,clk;reg[3:0]out;always@(posedgeclk)beginif(reset)out=0;//elseout=out+1;//endendmodule3.34`timescale1ns/1ns`includeadder4.vmoduleadder_tp;//reg[3:0]a,b;//regregcin;wire[3:0]sum;//wirewirecout;integeri,j;adder4adder(sum,cout,a,b,cin);//always#5cin=~cin;//cininitialbegina=0;b=0;cin=0;for(i=1;i16;i=i+1)#10a=i;//aend-2-initialbeginfor(j=1;j16;j=j+1)#10b=j;//bendinitial//begin$monitor($time,,,%d+%d+%b={%b,%d},a,b,cin,cout,sum);#160$finish;endendmodule3.44`timescale1ns/1ns`includecount4.vmodulecoun4_tp;regclk,reset;//regwire[3:0]out;//wireparameterDELY=100;count4mycount(out,reset,clk);//always#(DELY/2)clk=~clk;//initialbegin//clk=0;reset=0;#DELYreset=1;#DELYreset=0;#(DELY*20)$finish;end//initial$monitor($time,,,clk=%dreset=%dout=%d,clk,reset,out);endmodule3.5--moduleAOI(A,B,C,D,F);//AOI(ABCDF)inputA,B,C,D;//ABCDoutputF;//FVerilogHDL-3-wireA,B,C,D,F;//assignF=~((A&B)|(C&D));//endmodule5.1case41modulemux4_1(out,in0,in1,in2,in3,sel);outputout;inputin0,in1,in2,in3;input[1:0]sel;regout;always@(in0orin1orin2orin3orsel)//case(sel)2'b00:out=in0;2'b01:out=in1;2'b10:out=in2;2'b11:out=in3;default:out=2'bx;endcaseendmodule5.2modulecount(out,data,load,reset,clk);output[7:0]out;input[7:0]data;inputload,clk,reset;reg[7:0]out;always@(posedgeclk)//clkbeginif(!reset)out=8'h00;//0elseif(load)out=data;//elseout=out+1;//endendmodule5.3always`defineadd3'd0`defineminus3'd1`defineband3'd2`definebor3'd3`definebnot3'd4-4-modulealu(out,opcode,a,b);output[7:0]out;reg[7:0]out;input[2:0]opcode;//input[7:0]a,b;//always@(opcodeoraorb)//alwaysbegincase(opcode)`add:out=a+b;//`minus:out=a-b;//`band:out=a&b;//`bor:out=a|b;//`bnot:out=~a;//default:out=8'hx;//endcaseendendmodule5.4initialABC`timescale1ns/1nsmoduletest;regA,B,C;initialbeginA=0;B=1;C=0;#50A=1;B=0;#50A=0;C=1;#50B=1;#50B=0;C=0;#50$finish;endendmodule5.5begin-end`timescale10ns/1nsmodulewave1;regwave;parametercycle=10;initialbeginVerilogHDL-5-wave=0;#(cycle/2)wave=1;#(cycle/2)wave=0;#(cycle/2)wave=1;#(cycle/2)wave=0;#(cycle/2)wave=1;#(cycle/2)$finish;endinitial$monitor($time,,,wave=%b,wave);endmodule5.6fork-join`timescale10ns/1nsmodulewave2;regwave;parametercycle=5;initialforkwave=0;#(cycle)wave=1;#(2*cycle)wave=0;#(3*cycle)wave=1;#(4*cycle)wave=0;#(5*cycle)wave=1;#(6*cycle)$finish;joininitial$monitor($time,,,wave=%b,wave);endmodule5.721moduleMUX21_1(out,a,b,sel);inputa,b,sel;outputout;assignout=(sel==0)?a:b;//sel0out=aout=bendmodule5.821moduleMUX21_2(out,a,b,sel);inputa,b,sel;-6-outputout;regout;always@(aorborsel)beginif(sel==0)out=a;//elseout=b;endendmodule5.9modulenon_block(c,b,a,clk);outputc,b;inputclk,a;regc,b;always@(posedgeclk)beginb=a;c=b;endendmodule5.10moduleblock(c,b,a,clk);outputc,b;inputclk,a;regc,b;always@(posedgeclk)beginb=a;c=b;endendmodule5.1160BCDmodulecount60(qout,cout,data,load,cin,reset,clk);output[7:0]qout;outputcout;input[7:0]data;inputload,cin,clk,reset;reg[7:0]qout;always@(posedgeclk)//clkVerilogHDL-7-beginif(reset)qout=0;//elseif(load)qout=data;//elseif(cin)beginif(qout[3:0]==9)//9beginqout[3:0]=0;//05if(qout[7:4]==5)qout[7:4]=0;elseqout[7:4]=qout[7:4]+1;//51endelse//91qout[3:0]=qout[3:0]+1;endendassigncout=((qout==8'h59)&cin)?1:0;//endmodule5.12BCDmoduledecode4_7(decodeout,indec);output[6:0]decodeout;input[3:0]indec;reg[6:0]decodeout;always@(indec)begincase(indec)//case4'd0:decodeout=7'b1111110;4'd1:decodeout=7'b0110000;4'd2:decodeout=7'b1101101;4'd3:decodeout=7'b1111001;4'd4:decodeout=7'b0110011;4'd5:decodeout=7'b1011011;4'd6:decodeout=7'b1011111;4'd7:decodeout=7'b1110000;4'd8:decodeout=7'b1111111;4'd9:decodeout=7'b1111011;default:decodeout=7'bx;endcaseend-8-endmodule5.13casezmodulemux_casez(out,a,b,c,d,select);outputout;inputa,b,c,d;input[3:0]select;regout;always@(selectoraorborcord)begincasez(select)4'b???1:out=a;4'b??1?:out=b;4'b?1??:out=c;4'b1???:out=d;endcaseendendmodule5.14moduleburied_ff(c,b,a);outputc;inputb,a;regc;always@(aorb)beginif((b==1)&&(a==1))c=a&b;endendmodule5.15formodulevoter7(pass,vote);outputpass;input[6:0]vote;reg[2:0]sum;integeri;regpass;always@(vote)beginsum=0;VerilogHDL-9-for(i=0;i=6;i=i+1)//forif(vote[i])sum=sum+1;if(sum[2])pass=1;//4pass=1elsepass=0;endendmodule5.16for28modulemult_for(outcome,a,b);parametersize=8;input[size:1]a,b;//output[2*size:1]outcome;//reg[2*size:1]outcome;integeri;always@(aorb)beginoutcome=0;for(i=1;i=size;i=i+1)//forif(b[i])outcome=outcome+(a(i-1));endendmodule5.17repeat8modulemult_repeat(outcome,a,b);parametersize=8;input[size:1]a,b;output[2*size:1]outcome;reg[2*size:1]temp_a,outcome;reg[size:1]temp_b;always@(aorb)beginoutcome=0;temp_a=a;temp_b=b;repeat(size)//repeatsizebeginif(temp_b[1])//temp_b1outcome=outcome+temp_a;temp_a=temp_a1;//a-10-temp_b=temp_b1;//bendendendmodule5.18moduleloop1;//1integeri;initialfor(i=0;i4;i=i+1)//forbegin$display(“i=%h”,i);endendmodulemoduleloop2;//2integeri;initia