Altium-Designer设计教程-19

第1页共38页DB31AlteraCycloneIIF672第一部分原理图目录树1DB31_TOP.SchDoc1.1PSU.SchDoc1.1PSU_MAX1831.SchDoc1.2DB31_Hardware_Kit.SchDoc1.2.DB_MOUNTS.SchDoc1.3DB_ByPass.SchDoc1.4DB_Common.SchDoc1.4.1DEVICES.SchDoc1.4.1.1FPGA.SchDoc1.4.1.1.1FPGA_NonIO.SchDoc1.4.1.1.2Bypass_FPGA_1V2.SchDoc1.4.1.1.3Bypass_FPGA_1V3.SchDoc1.4.1.1.41WB_DS2406_EPROM.SchDoc1.4.2NB2_CommonMemory_Terminaiton.SchDoc1.4.3DB_LEDS.SchDoc1.4.4NB2_CommonMemory.SchDoc1.4.4.1FLASH_S29GL256N11FF1V10_16M×16.SchDoc1.4.4.2SDRAM_MT48LC16M16A2TG_16M×32.SchDoc1.4.4.3SRAM_256K×32_TSOP44_1.SchDoc1.4.5MotherBooardConnectors.SchDoc1.4.6SRAM_256K×16_TSOP44.SchDoc1.5DB31.PcbDoc1.6DB31_Panel.PcbDoc第2页共38页第一部分原理图1DB31_TOP.SchDocU_DB_CommonDB_CommonU_PSUPSU.SCHDOCU_Bypass_BoardDB_BypassU_DB31_Hardware_KitDB31_Hardware_Kit.SchDoc第3页共38页1.1PSU.SchDoc3V31V25V0iPWRNETiPWRNETiPWRNETAGNDGNDiPWRNETiPWRNET12NT7TP13V3TP35V0TP41V2TP0GNDiPWRNETTP2GNDGNDU_PSU_MAX1831_1V2_ALTPSU_MAX1831_1V2_ALTSharedBypassCapsGND3V3C23_CM10uF10VC24_CM10uF10V1V2第4页共38页1.1PSU_MAX1831.SchDocGNDGNDAGNDAGNDGNDVfiltGNDAGND1V25V0GNDGNDREF_1V2FBLXCOMPTOFFC6_PS22uF10VC1_PS22uF10VC3_PS220uF10VC8_PS10uF10VC2_PS470pF50VC4_PS2.2uF10VC5_PS10uF10VC7_PS1uF25VR2_PS10R1%R3_PS27K1%R1_PS2K71%R4_PS2K71%R5_PS100K1%LX1LX3LX14LX16IN2IN4SHDN5COMP6TOFF7FB8AGND9REF10FBSEL11VCC12PGND13PGND15U1_PSMAX1831EEEL1_PS2u2,15A,4R2,SMD第5页共38页1.2DB31_Hardware_Kit.SchDocU_MOUNTSDB_MOUNTSPrintedCircuitBoard(Bare)PCB1DB31BlankPCB第6页共38页1.2.DB_MOUNTS.SchDocMH1MOUNTINGHOLE3MMMH2MOUNTINGHOLE3MMMH3MOUNTINGHOLE3MMPurPerLogoTop1PurPerPurPerLogoBot1PurPerMH1MOUNTINGHOLE3MMMH2MOUNTINGHOLE3MMMH3MOUNTINGHOLE3MM第7页共38页1.3DB_ByPass.SchDocGND3V3C1_MB220uF10VC2_MB220uF10VThesedecouplingcapacitorsareintendedtoassistthevoltagerailsonthePCB-wherethedecouplingcapacitorsfortheFPGAarenotclose.第8页共38页1.4DB_Common.SchDocSTATUS_LEDSRAM1STATUS_LEDSRAM2BUSDAU_RESET_SWBUZZERONE_WIRE_DBIDONE_WIRE_DB_PBONE_WIRE_PIO1JTAGSWDIPUSERIOEXT_AEXT_BEXT_CUSER_LEDSPII2CCANRS232KEYBOARDMOUSETFTPROGRAMCLOCKSSLEEP_NU_DEVICESDEVICES.SchDocSRAMU_SRAM_K6R4016V1D-TC10T_256Kx16SRAM_256Kx16_TSOP44SRAMU_SRAM_K6R4016V1D-TC10T_256Kx16SRAM_256Kx16_TSOP44MEMU_Memory_CommonBus_DaughterBoardNB2_CommonMemoryMEMU_CommonMemory_TerminationNB2_CommonMemory_TerminationSTATUS_LEDU_DaughterBoard_LEDSDB_LEDSDAU_RESET_SWBUZZERONE_WIRE_DBIDONE_WIRE_DB_PBONE_WIRE_PIO1JTAGSWDIPUSERIOEXT_AEXT_BEXT_CUSER_LEDSPII2CCANRS232KEYBOARDMOUSETFTPROGRAMCLOCKSSLEEP_NU_MotherBoardConnectorsDB_MotherBoardConnectorsTopLevelSchematicForDaughterBoardDesignBothFPGA-OnlyandFPGA+MCUThisDeviceSheetisthesameforalldesigns.Itreliesonbeinginstantiatedinaprojectthatcontainsadevice-specificsheetnamedDEVICES.SchDoc.第9页共38页1.4.1DEVICES.SchDocSRAM1SRAM2MEM_COMMONDAU_RESET_SWBUZZERONE_WIRE_DBIDONE_WIRE_DB_PBONE_WIRE_PIO1JTAGSWDIPUSERIOEXT_AEXT_BEXT_CUSER_LEDSPII2CCANRS232KEYBOARDMOUSETFTPROGRAMCLOCKSSTATUS_LEDU_FPGAFPGA.SCHDOCDIPUSER_LEDUSERIOI2CKEYBOARDMOUSERS232SPITFTEXT_AEXT_BEXT_CONE_WIRE_DB_PBONE_WIRE_DBIDONE_WIRE_PIO1STATUS_LEDBUSSRAM1SRAM2CLOCKSPROGRAMJTAGDAU_RESET_SWSWBUZZERCANSLEEP_NDeviceSpecificSectionofDaughterBoardDesignThisschematicsheet(plusanychildsheets)willcontainthedevicespecificpartsofanydaughterboarddesigns.ThiswillincludeanyFPGAorMCUdevicesaswellasdedicatedpowersupplies,connectorsetc.第10页共38页1.4.1.1FPGA.SchDocFPGA_TCKFPGA_TDIFPGA_TMSFPGA_TDOFPGA_PROGRAMFPGA_M0FPGA_M1FPGA_CCLKFPGA_DONE3V3FPGA_PROGRAMFPGA_TDOFPGA_INITFPGA_DONEGNDFPGA_ID3FPGA_ID0FPGA_ID1FPGA_ID2STATUS_LEDFPGA_ID=0x1(Altera)TMSCONF_DONEMSEL1DCLKMSEL0DATA0TCKnSTATUSTDInCONFIGTDOU_FPGA_PowerFPGA_NonIO.SchDocFPGA_DONE3V3FPGA_DINFPGA_INITFPGA_CCLKFPGA_CLK1iFPGACONFiFPGACONFiFPGACONFiFPGACONFiFPGACONFiFPGACONFiFPGACONFiFPGACONFiFPGACONFiFPGACONFiFPGACONFCAN_TXDSRAM1_NWEEXTEND_C48EXTEND_C44EXTEND_C40FPGA_CLKREF_CLKEXTEND_C49EXTEND_C46EXTEND_C42CAN_RXDRS232_RTSNEXUS_TDOEXTEND_C36EXTEND_C34EXTEND_C32EXTEND_C30EXTEND_C37EXTEND_C35EXTEND_C33EXTEND_C31SRAM1_A5GNDBUS_SDRAM_FEEDBACKCLK0,LVDSCLK0pINPUTN2CLK1,LVDSCLK0nINPUTN1CLK2,LVDSCLK1pINPUTP2CLK3,LVDSCLK1nINPUTP1CLK15,LVDSCLK7pINPUTAC13CLK14,LVDSCLK7nINPUTAD13CLK13,LVDSCLK6pINPUTAF14CLK12,LVDSCLK6nINPUTAE14CLK7,LVDSCLK3nINPUTP26CLK6,LVDSCLK3pINPUTP25CLK5,LVDSCLK2nINPUTN26CLK4,LVDSCLK2pINPUTN25CLK8,LVDSCLK4nINPUTB13CLK9,LVDSCLK4pINPUTA13CLK10,LVDSCLK5nINPUTC13CLK11,LVDSCLK5pINPUTD13U1MEP2C35F672C8BANK8IO,LVDS200n(DEV_OE)AE4IO,LVDS200p,DM1B/_AF4IO,LVDS199p,DQ1B7/_AC5IO,LVDS199n,DQ1B6/_AC6IO,LVDS198p,DQ1B5/_AD4IO,LVDS198n,DQ1B4/_AD5IO,LVDS197p,(CDPCLK2/DQS1B)/(CDPCLK2/DQS1B)AE5IO,LVDS197nAF5IO,LVDS196p,DQ1B3/_AD6IO,LVDS196nAD7IO,LVDS195pV10IO,LVDS195nV9IO,VREFB8N1AC7IOW8IO,LVDS194pW10IO,LVDS194n,DQ1B2/_Y10IO,DQ1B1/_AB8IO,LVDS193p,DQ1B0/_AC8IO,LVDS193n,(DM3B/BWS#3B)/(DM3B1/BWS#3B1)AD8IO,LVDS192p,DQ3B8/DQ3B17AE6IO,LVDS192n,DQ3B7/DQ3B16AF6IO,DQ3B6/DQ3B15AA9IO,LVDS191p,DQ3B5/DQ3B14AA10IO,LVDS191n,DQ3B4/DQ3B13AB10IO,LVDS190p,DQ3B3/DQ3B12AA11IO,LVDS190n,DQ3B2/DQ3B11Y11IO,LVDS189p,DQ3B1/DQ3B10AE7IO,LVDS189n,DQ3B0/DQ3B9AF7IO,LVDS188p,(DPCLK2/DQS3B)/(DPCLK2/DQS3B)AE8IO,LVDS188nAF8IO,LVDS187pW11IO,LVDS187nW12IO,LVDS186p,(DM5B/BWS#5B