veriloga

Verilog-ALanguageByWilliamVidesModfiedbyGeorgeEngelDifferencebetweenDigitalandAnalogDesignAlways@(enable)beginvalid=1’b0;//dowritecycleaddr_lines=addr;data_lines=data;@(negedgeclk)beginvalid=1’b1;endendTopDownRefinedfromHDLLevelBottom-UpTransistorlevelBehavioralGateSwitchCircuitHigherlevelofabstractionVerilog-AasanextensionofSpiceAnalogSystemDescriptionandsimulationStructuralDescription•amoduleiscomprisedofotherchildmodulesBehavioralDescription•descriptionsinaprogrammaticfashionwiththeVerilog-Alanguage•ThemoduleisdefinedintermsofthevaluesforeachsignalMixed-levelDescriptions•CombinebothStructuralandBehavioralDescriptionsModemExamplemodemmodulatorchanneldemodulatorThemodemsystemismadeupof1)themodulator2)achannel3)thedemodulatorStructuralDescriptionhierarchyModule:qamInstance:modmodule:qam_modInstance:c1module:channelInstance:demodmodule:qam_demodStructuralDescriptionoftheModemSystem//VerilogAdefinitionofthemodemSystem`include“std.va”modulemodem(dout,din)’inoutdout,din;electricaldout,din;parameterrealfc=100.0e6;electricalclk,cin,cout;qam_mod#(.carrier_freq(fc))mod(cin,din,clk);channelc1(cout,cin);qam_demod#(.carrier_freq(fc))demod(dout,cout,clk);endmoduleStructuralDescriptionTypeofmoduleinstanceNameoftheinstancecreatedqam_mod#(.carrier_freq(fc))mod(cin,din,clk);Parameternameinchild(qam_mod)moduleassignedas:carrier_freq=fc16_QAMmodemExample2-bitd2aSerin_parout2-bitd2aaqAsin(2pifct+pi/4)didqaiAcos(2pifct+pi/4)dinmoutA(t)cos(2pifct+0(t))VerilogAmixedSignaldefinitionof16-QAMmodulatormoduleqam_mod(mout,din,clk);inoutmout,din,clk;electricalmout,din,clk;parameterrealfc=100.0e6;electricaldi1,di2,dq1,dq2;electricalai,aq;serin_paroutsipo(di1,di2,dq1,dq2,din,clk);d2ad2ai(ai,di1,di2,clk);d2ad2aq(aq,dq1,dq2,clk);realphase;VerilogAmixedSignaldefinitionof16-QAMmodulatoranalogbeginphase=2.0*`M_PI*fc*$realtime()+`M_PI_4;V(mout)+0.5*(V(ai)*cos(phase)+V(aq)*sin(phase));endendmoduleThebehavioraldefinitionoftheQAMmodulationisdefinedThesignalsaiandaqaretheoutputsofthe2-bitD/AconvertersTypeofanalogsystemsConservativeSystems•useofKirchoff’slaws•ElectricalSystemsuseKVLandKCL•AnyconservativeSystemuseKPLandKFL–appliedtobranchesSignalFlowSystems•onlypotentialisassociatedwitheverynode•unidirectional•notionofports(input/output)ConservativeSystemsDevice+-VInaconservativesystemthechargesorsignalscanenteraparticulardeviceinbothways.SignalFlowSystemsinOutAmplifierInsignalflowsystemsasignalcanonlyenteradeviceinonewayonly.WhatisSimulation?simulationisaprocessinwhichasystemofnonlinearordinarydifferentialequationsissolvedthisequationsarenotinputdirectly,butderivedfromeachofthemodelsthatareinterconnectedinthenetlistWhatitmeanstotheuser?Totheuserasimulationisessentiallyasoftwareversionofanoscilloscopeorlogicanalyzer.Asimulationisatechniquebywhichtheuseraskquestionsandreceivesanswersfromaprogram.Thequalityoftheanswersdependsonthequalityofthequestions.AnalogSystemSimulationTheStandardapproachtoanalogcircuitsimulationinvolves•formulatethedifferential-algebraicequationsforthecircuit•applyingimplicitintegrationmethodstothesequenceofnonlinearalgebraicequations•iterativemethodssuchasNewton-Raphsontoreducetoasetoflinearequations•usingsparsematrixtechniquestosolvethelinearequationsAnalogModelPropertiesTheVerilog-Alanguagecanbeusedtorepresentdifferenttypesofbehaviorstheseinclude•Linear•Nonlinear•Piecewiselinear•Integrodifferential•Event-drivenAnalogAnalogOperatorsTheVerilog-Alanguagedefinesanalogoperatorsfor•TimeDerivative•TimeIntegral•Lineartimedelay•Discretewaveformfilters•LaPlaceTransformfilters•Z-transformfiltersTimeDerivativeOperatorTheddtOperatorcomputesthetimederivativeofitsarguments•ddt(expression)InDCanalysistheddtoperatorreturnsazero.Applicationoftheddtoperatorresultsinazeroattheorigin.TimeIntegralOperatorTheidtoperatorcomputesthetimeintegralofitsarguments•idt(expression,ic,reset)WhenspecifiedwithinitialconditionstheidtoperatorreturnsthevalueoftheinitialconditioninDC.Withoutinitialconditions,idtmultipliesitsargumentbyinfinityinDCanalysis.TimeIntegralOperatorTheOptionalargumentRESETallowsresettingoftheintegratortotheinitialconditionorICvalue.Applicationoftheidtoperatorresultsinapoleattheorigin.DelayOperatorDelayoperatorimplementsatransportorlineartimedelayforcontinuouswaveforms•delay(expression,dt)TheparameterDTmustbepositiveTheeffectofthedelayoperatorinthetimedomainistoprovideadirecttimetranslationoftheinputTransitionOperatorThetransitionoperatorsmoothsoutpiece-wiseconstantwaveforms.Thetransitionfilterisusedtoimitatetransitionsanddelaysondiscretesignals•transition(expression,dt,tr,tf)Theinputexpressiontothetransitionoperatormustbedefinedintermsofdiscretestates.TransitionOperatorTheparametersdt,tr,tfareoptional•tr-transitionrise•tf-transitionfall•dt-changeintimeifdtisnotspecifiedthenitistakentobezeroifthevaluefortrisspecifiedthesimulatorwilluseitforboththeriseandfalltimes.TransitionOperatorWhenriseandfalltimesarelongerthanthespecifieddelay•ifthenewfinalvaluelevelisbelowthecurrentvaluethetransitionOperatorusestheolddest