Analysis-of-the-PLL-jitter-due-to-power-ground-and

2404IEEETRANSACTIONSONCIRCUITSANDSYSTEMS—I:REGULARPAPERS,VOL.51,NO.12,DECEMBER2004AnalysisofthePLLJitterDuetoPower/GroundandSubstrateNoisePayamHeydari,Member,IEEEAbstract—Phase-lockedloops(PLLs)inradio-frequency(RF)andmixedanalog-digitalintegratedcircuitsexperiencesub-stratecouplingduetothesimultaneouscircuitswitchingandpower/ground(P/G)noisewhichtranslatetoatimingjitter.Inthispaper.ananalysisofthePLLtimingjitterduetosubstratenoiseresultingfromP/Gnoiseandlarge-signalswitchingispre-sented.AgeneralcomprehensivestochasticmodelofthesubstrateandP/Gnoisesourcesinverylarge-scaleintegrationcircuitsisproposed.Thisisfollowedbycalculationofthephasenoiseoftheconstituentvoltage-controlledoscillator(VCO)intermsofthestatisticalpropertiesofsubstrateandP/Gnoise.ThePLLtimingjitteristhenpredictedinresponsetotheVCOphasenoise.Ourmathematicalmethodisutilizedtostudythejitter-inducedP/GnoiseinaCMOSPLL,whichisdesignedandsimulatedina0.25-mstandardCMOSprocess.AcomparisonbetweentheresultsobtainedbyourmathematicalmodelandthoseobtainedbyHSPICEsimulationprovetheaccuracyofthepredictedmodel.IndexTerms—Cyclostationarynoise,jitter,phase-lockedloop(PLL),phasenoise,power/groundbounce,randomprocess,ringoscillator,substratenoise,voltage-controlledoscillator(VCO).I.INTRODUCTIONPHASE-lockedloops(PLLs)areubiquitouscircuitblocksinRFandmixed-signalintegratedcircuits.Theyareex-tensivelyutilizedason-chipclockgeneratorstosynthesizeandde-skewahigherinternalfrequencyfromtheexternallowerfre-quency[1].Indatacommunications,seriallinks,anddisk-drivereadchannels,PLLsystemsarealsousedasclockrecoverysys-tems[1].Inbroadbandopticalcommunicationnetwork,theyareusedasclockanddatarecovery(CDR)togeneratetheclockandretimethedatafromthereceivedelectricalsignal[2]–[4].Inwirelesscommunications,theyareutilizedasfrequencysyn-thesizerstosynthesizeanaccurateoutputfrequency[1].Inalloftheaboveapplications,therandomtemporalvariationofthephase,orjitter,isoneofthemostcriticalperformanceparam-eters.Jitterrepresentsthedeviationofzerocrossingsofape-riodicwaveformfromtheiridealpointsonthetimeaxis.ThedeviationofzerocrossingsofthewaveformsynthesizedbythePLLcausesthesetup-andhold-timeviolationsindigitalcircuitsthatusethePLLasclockgenerator,andtherefore,leadstodatatransmissionerrorsandfunctionalityfailure.Theever-increasingdemandtointegrateallcircuitcompo-nentsonthesamechipgivesrisetosomecriticalnoisetoleranceManuscriptreceivedOctober19,2003;revisedMarch11,2004.ThispaperwasrecommendedbyAssociateEditorH.E.Graeb.TheauthoriswiththeDepartmentofElectricalEngineeringandComputerScience,UniversityofCalifornia,Irvine,CA92697-2625USA(e-mail:[e-mail]).DigitalObjectIdentifier10.1109/TCSI.2004.838240requirementsforsensitiveanalogcircuits(e.g.,PLLcircuits)in-sidethechip.Infact,oneofthegreatestchallengesinthedesignofasystem-on-a-chip(SOC)istheneedtoplacesensitiveanalogcircuitsandlargecomplexdigitalsignalprocessingcomponentsonthesamedie.Duetothehighlevelofinteractionsbetweenthenoisydigitalblockswiththenoise-sensitiveanalogportionofthesystemthroughvariouspropagationmechanisms,itishighlypossiblethatthelarge-signalswitchingtransientsofthedigitalcircuitscorrupttheperformanceoftheanalogsub-blocks.InanSOC,couplingfromdigitalcircuitsintoanalogcompo-nentsmostlypropagatesthroughthecommonsubstrateandpower/ground(P/G)rails.SubstrateandP/GcouplingsdegradethesignalintegrityofthePLLinmixedanalog-digitalintegratedcircuitswherethousandsofdigitalgatesmayinjectnoiseintothesubstrateandglobalP/Gwires,especiallyduringclocktran-sitions,introducinghundredsofmillivoltsofdisturbanceinthesubstratepotential[5]–[8].Thepeakamplitudeandpulse-widthofsubstrateandP/Gnoisesourcesaremultipleordersofmag-nitudelargerthanthoseofdevicenoisesourcesinhigh-speedmixedanalog-digitalintegratedcircuits,therebymakingsub-strateandP/GnoisesourcesdominatetheperformanceofPLLcircuits.Henceforth,PLLcircuitsmustbedesignedtooperaterobustlyinthepresenceoftheP/Gandsubstratenoise.Recently,interestingapproachesoncharacterizationofthephasenoiseinelectricaloscillatorsduetodevicenoisesourceshavebeenproposed[9]–[11].While[9]usedalineartime-invariant(LTI)modeltodescribethebehaviorofphasenoiseinoscillators,[10]proposedamoreaccuratelineartime-varying(LTV)modeltocharacterizetheoscillatorphasenoise.[11]studiedthephasenoiseofoscillatorsbyderivinganonlinearstochasticdifferentialequationforphaseerror,andsolvingthisequationinthepresenceofrandomperturbations.Herzeletal.addressedthetimingjitterofoscillatorsduetothepowersupplyandsubstratenoise[12].Accordingto[12],anoscillatorsubjecttosupplyandsubstratenoiseismodeledasavoltage-controlledoscillator(VCO)withdifferentcontrolvoltages,andtherefore,thejittereffectisviewedasfrequency-modulatedsinusoidalwaveform.Thestudyproposedby[12],however,suffersfromanimportantdrawback,wheretheoscillatorcircuitinthepres-enceofinherentlystochasticsubstrateandP/Gnoisesourcesistreatedasadeterministicsystem.[13]proposedamoregeneralmodelforthePLLaccountingforthetime-varyingeffectsofthePLL.Similartoopen-looposcillators,closed-loopPLLcircuitsarealso