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PredictableSuccess2007.12ICCompilerHierarchicalFlowUpdateShoukyouWang©2006Synopsys,Inc.(2)PredictableSuccessAgendaICCHierarchicalFlowOverview•DesignPlanning•BlockImplementation•TopLevelImplementation•Lab©2006Synopsys,Inc.(3)PredictableSuccessICCDesignplanningDesignPrototyping(Timing,Routability,PowerIntegrity)DetailedFloorplaningPhysicalHierarchyCreationTopCellFloorplan/PowerPlanICCHierarchicalMethodologyDesignGateLevelNetlistTimingConstraintsFloorplanConstraintsLogicalandPhysicalLibraryBlockCellFloorplan/PowerPlanTimingBudgetsDetailImplementationDetailImplementation©2006Synopsys,Inc.(4)PredictableSuccessICCHierarchicalMethodologyICCBlock-levelImplementationClock_optCompletedBlockICCTop-levelImplementationPlace_optRoute_optPropagateSDCClock_optonILMRoute_optonILMReplaceCELwtFRAMPlace_optonILMILMModelgenerationFRAMModelgeneration***EarlyExplorationusingILMLoadBlock&SDCLoadTOP&ILM****optional©2006Synopsys,Inc.(5)PredictableSuccessHierarchicalDesignDatabaseManagementFullChipDesignLibChipCelReferenceFullChipDesignLibTopCelBlockCelBlockCelDesignPlanningTopDesignLibTopCelBlockDesignLibBlockCelBlockDesignLibBlockCelBlockDesignLibBlockCel/FRAM/ILMBlockDesignLibBlockCel/FRAM/ILMTopDesignLibTopCelBlockImplementationSplitDesign©2006Synopsys,Inc.(6)PredictableSuccessAgenda•ICCHierarchicalFlowOverviewDesignPlanning•BlockImplementation•TopLevelImplementation•Lab©2006Synopsys,Inc.(7)PredictableSuccessICCDesignPlanningVFPlacement/RefinementPowerNetworkSynthesis/AnalysisPrototypeRoutePlanGroupShapingVirtualFlatPlacementInitializeFloorplanReadNetlist/DesignConstraintscreate_mw_libopen_mw_libread_verilog_to_cel$netlist_fileset_tlu_plus_filesread_sdc$sdc_fileread_io_constraintsio.tdfinitialize_floorplanset_fp_placement_strategyreport_fp_placement_strategycreate_fp_placementcreate_plan_groupshape_fp_blocksCreate_fp_plan_group_paddingcreate_fp_placementconnect_pg_netsset_fp_rail_constraints#set_fp_block_ring_constraints#set_fp_rail_region_constraintssynthesize_fp_railCommit_fp_rail#preroute_standard_cellsset_parameter-namereadPlanGroup-value1route_fp_proto…©2006Synopsys,Inc.(8)PredictableSuccessICCDesignPlanningSave/SplitDesignsRefinePinAssignmentCommitHierarchyPinAssignmentSetPinAssignmentConstraintsTimingBudgetingInPlaceOptimizationreport_timingset_dont_touch_placement{hard_macro_list}optimize_fp_timingset_fp_pin_constraints-allow_feedthroughs[off|on]…report_fp_pin_constraintsset_parameter-namereadPlanGroup-value1route_globalanalyze_fp_routing–finalizeextract_rcreport_timingcheck_fp_timing_environmentallocate_fp_budgetscommit_fp_plan_groupscheck_fp_pin_assignmentcheck_fp_pin_alignmentplace_fp_pinssave_mw_cel–hierarchysplit_mw_lib©2006Synopsys,Inc.(9)PredictableSuccessICCDesignPlanning©2006Synopsys,Inc.(10)PredictableSuccessICCDesignPlanning•Useread_verilog_to_celtoreadverilognetlistUseuniquify_fp_mw_celfornon-uniquifiednetlist•optimize_fp_timingdoesvirtualroutebasedoptimization•Useplangroupawareroutingtoimprovetoplevelcongestionanalysisset_parameter-namereadPlanGroup-value1•Pinassignment(pincutting)decidespinlocationbasedonintersectionofglobalroutesandplangroupboundaries(pincutting)Incrementalpinassignmentallowedaftercommithierarchy•DonotproceedtopinassignmentbeforesolvingcongestionissuesRoutingbasedpinassignmentcantakelongruntimeandgeneratepoorresultoncongesteddesigns•Usesave_mw_cel–hierarchicaltosavealltheopencells©2006Synopsys,Inc.(11)PredictableSuccessFeedthroughGeneration•AdditionalstepsneedediffeedthroughisinvolvedinICChierarchicalflowCheckfeedthroughcandidatesbeforepinassignment•Useanalyze_fp_routingBufferfeedthroughnetsafterpincuttingsetfpopt_env_feedthru_buftrueoptimize_fp_timingCheckdesignforfeedthroughconnectionsbeforeICCimplementation•Usecheck_designandsearchfor“LINT-29”“LINT-31”warningsControloptimizationcommandstoinsertbufferonfeedthroughnets•set_fix_multiple_port_nets–all©2006Synopsys,Inc.(12)PredictableSuccessAgenda•ICCHierarchicalFlowOverview•DesignPlanningBlockImplementation•TopLevelImplementation•Lab©2006Synopsys,Inc.(13)PredictableSuccessICCBlockImplementationFRAMGenerationILMGenerationRoute_optClock_optPlace_optLoadDesign/SDCopen_mw_celset_tlu_plus_filecheck_designset_fix_multiple_port_nets–allremove_sdcread_sdcremove_propagated_clock[all_clocks]set_dont_touch_placement{hard_macro_list}set_pnet_optionsset_ideal_network[all_fanout-flat-clock_tree]place_optclock_opt-only_cts-no_clock_routeremove_ideal_network[all_fanout-flat-clock_tree]set_fix_hold[all_clocks]clock_opt-only_psyn-no_clock_routeroute_group-all_clock_netsset_si_optionsset_route_optionsroute_optsave_mw_celcreate_ilm–keep_parasitic–keep_full_clock_treecreate_macro_fram©2006Synopsys,Inc.(14)PredictableSuccessICCBlockImplementation©2006Synopsys,Inc.(15)PredictableSuccessICCBlockImplementation•FixholdtimeviolationsafterCTS•Useset_si_optiontoturnonSIoptionsbeforeroute_opt•Usecreate_ilm–include_xtalk–keep_full_clock_treetostoreSIinformationandlocalclocktreeinILM•create_ilmdirectlysavesILM,noneedtousesave_mw_cel(since2007.03)•Blocklevelflowfo
本文标题:ICC-hier-flow-200712-092007
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