数字电子技术期末试卷

重庆大学试卷教务处07版第1页共3页重庆大学数字电子技术I(双语)课程试卷2006~2007学年第2学期开课学院：通信工程学院课程号：16004735考试日期：考试方式：考试时间：120分钟题号一二三四五六七八九十总分得分注：1.大标题用四号宋体、小标题及正文推荐用小四号宋体；2.按A4纸缩小打印I.Multiplechoice(1pts/ea,15ptstotal)1)HowistheinvalidstateproblemassociatedwiththeS-Rflip-flopovercome?a)TheRterminaliseliminated.b)TheRinputisfedthroughaninverter.c)Asingleinputterminalisused(D).d)BothBandCarecorrect.2)Thisisthetimingdiagramfora2-input________gate.a)NANDb)ANDc)Exclusive-ORd)OR3)WhatisthemeaningofRAM,andwhatisitsprimaryrole?a)RandomAccessMemory;itismemorythatisusedforshort-termtemporarydatastoragewithinthecomputer.b)ReadilyAvailableMemory;itisthefirstlevelofmemoryusedbythecomputerinallofitsoperations.c)RandomAccessMemory;itismemorythatcanbereachedbyanysub-systemwithinacomputer,andatanytime.d)ResettableAutomaticMemory;itismemorythatcanbeusedandthenautomaticallyreset,orcleared,afterbeingreadfromorwrittento..4)WhichruleofBooleanalgebradoestheexamplebelowrepresent?a)A+1=1b)A∙0=0c)A+0=Ad)A∙1=A5)Thecircuitshownbelowis________.a)decadecounterb)BCDcounterc)Johnsoncounterd)ringcounter6)Thecircuitbelowismostlikelya________.a)full-adderb)demultiplexerc)multiplexerd)comparator7)Foranegative-logicpulse,thetrailingedgeisthe________.a)negative-goingedgeb)positive-goingedgec)HIGH-to-LOWtransitiond)fallingedge8)The2'scomplementofbinary110110is________.a)0010012b)0010102c)1101002d)10101029)WhichofthefollowingstatementsbestdescribestheoperationofanUP/DOWNSYNCHRONOUSCOUNTER?a)Thecountercanbereversed,butmustbeRESETbeforecountingintheotherdirection.b)Ingeneral,thecountercanbereversedatanypointinitscountingsequence.c)Thecountercancountineitherdirection,butmustcontinueinthatdirectiononcestarted.d)Thecountsequencecannotbereversed,onceithasbegun,withoutfirstresettingthecountertozero.命题人：组题人：审题人：命题时间：教务处制学院专业、班年级学号姓名公平竞争、诚实守信、严肃考纪、拒绝作弊封线密重庆大学试卷教务处07版第2页共3页Figure5-110)WhichofthefollowinglogicexpressionsrepresentsthelogicdiagraminFig5-1?a)ABBAXb)BAABXc)BABAXd)ABABX11)Foranidealdigitalpulse,transitiontimesare________.a)infinite;b)measuredbetween0and90%oftheamplitude;c)measuredbetween10%to90%oftheamplitude;d)zero;12)Whenperformingbinaryadditionusingthe2'scomplementmethod,an________canoccurif________areofthesame________;theerrorisindicatedbya(n)______.a)overflow,bothnumbers,sign,incorrectsignbitb)error,bothnumbers,magnitude,negativesignc)overflow,signs,magnitude,incorrectsumd)error,thesigns,polarity,incorrectpolarity13)WhichofthefollowingcombinationscannotbecombinedintoKarnaugh-mapgroups?a)Cornersinthesamecolumn;b)Cornersinthesamerow;c)Overlappingcombinations;d)Diagonalcorners;14)Apositiveedge-triggeredJ-Kflip-flopisusedtoproduceatwo-phaseclock.However,whenthecircuitisoperateditproduceserraticresults.Closeexaminationwithascoperevealsthepresenceofglitches.Whatcausestheglitches,andhowmighttheproblembecorrected?a)ThePRESETandCLEARterminalsmayhavebeenleftfloating;theyshouldbeproperlyterminatedifnotbeingused.b)TheproblemiscausedbyaraceconditionbetweentheJandKinputs;aninvertershouldbeinsertedinoneoftheterminalstocorrecttheproblem.c)AraceconditionexistsbetweentheQandQoutputstotheANDgate;theANDgateshouldbereplacedwithaNANDgate.d)AraceconditionexistsbetweentheCLOCKandtheoutputsoftheflip-flopfeedingtheANDgate;replacetheflip-flopwithanegativeedge-triggeredJ-Kflip-flop.15)WhenbothinputsofaJ-Kedge-triggeredFFarehigh,andtheclockcycles,theoutputwilla)notchange;b)toggle;c)remainunchanged;d)beinvalidII.Computeandfillintheblank(3pts/ea,30ptstotal)1)Howmanyinputlineswouldberequiredfora1-of-8decoder?2)Supposethata3-digitBCDdigital-to-analogconverterhasafull-scaleoutputof49.95mA.WhatisthepercentageresolutionoftheDAC?3)Withcurrenttechnology,a12-bitflashA/Dconverterwouldrequire__________comparators.4)Howmanytruthtableentriesarenecessaryfora4inputcircuit?5)GiventheBooleanexpression)(GDLMNXandthevaluesL=1,M=0,N=1,D=1,andG=0,thevalueofXis:6)Aretriggerableone-shothasapulsewidthof10mS;3mSafterbeingtriggered,anothertriggerpulseisapplied.Theresultingoutputpulsewillbe________ms7)Theequationfortheoutputfrequencyofa555timeroperatingintheastablemodeis:f=1.44/((R1+2*R2)*C).WhatvalueofCwillberequiredifR1=R2=1Kandf=1KHz?8)AcertainIClogicgatedraws1.8mAwhenitsoutputisHIGHand3.8mAwhenitsoutputisLOW.Assumea50%dutycycleandcalculatetheaverageIcccurrentdrain.9)Acertainlogicdevicehasthefollowingspecifications:VOL(max)=0.5v,VIL(max)=0.9v,VOH(min)=2.6,andVIH(min)=2.1v.Determinethelow-statedcnoisemarginFigure8-910)WhatisthemodulusofthecountershowninFigure8-9?重庆大学试卷教务处07版第3页共3页III.forthecircuitbelow,ploteachoutputwaveformfortheinputsshown.(5pts)IV.Iftheinputwaveformsareappliedtothecircuitbelow,sketchtheoutputwaveform(5pts)V.Designa7-segmentdecoderlogicforsegmenta.(12pts)VI.Designacountertoproducethefollowingbinarysequence.UseJ-Kflip-flops.(15pts)0,9,1,8,2,7,3,6,4,5,0,…fortruncatedstates,checkauto-reentryproperty.VII.A555timerisconfiguredtorunasanastablemultivibratorasshownbelow,determinefollowingparameters:(8pts)Given:R1R2C=15.4pFFind:f,tH,tL,DutycycleVIII.Theshiftregisterisgivenbelow,theSERisa0.developdata-output