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当前位置:首页 > 电子/通信 > 电子设计/PCB > 超完美VHDL数码管显示键值-PS2键盘控制实验
共四个文件:顶层,分频,读键,显示。绝对正确。libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_ARITH.ALL;useIEEE.STD_LOGIC_UNSIGNED.ALL;----Uncommentthefollowinglibrarydeclarationifinstantiating----anyXilinxprimitivesinthiscode.--libraryUNISIM;--useUNISIM.VComponents.all;entitytopisport(clr:instd_logic;clk:instd_logic;ps2clk:instd_logic;ps2data:instd_logic;a_to_g:outSTD_LOGIC_VECTOR(6downto0);sel:outSTD_LOGIC_VECTOR(3downto0);dp:outSTD_LOGIC);endtop;architectureBehavioraloftopissignalclk4,sclk:std_logic;signaldat:std_logic_vector(15downto0);componentdivclkisport(clk:instd_logic;------50MHZclk400:outstd_logic;-------400KHZscanclk:outstd_Logic);endcomponent;componentkey_boardisport(clr:instd_logic;clk400:instd_logic;--400KHZps2clk:instd_logic;ps2data:instd_logic;dataout:outstd_logic_vector(15downto0));endcomponent;componentdispisport(clr:instd_logic;scanclk:instd_logic;datain:instd_logic_vector(15downto0);a_to_g:outSTD_LOGIC_VECTOR(6downto0);sel:outSTD_LOGIC_VECTOR(3downto0);dp:outSTD_LOGIC);endcomponent;begininst1:divclkportmap(clk,clk4,sclk);inst2:key_boardportmap(clr,clk4,ps2clk,ps2data,dat);inst3:dispportmap(clr,sclk,dat,a_to_g,sel,dp);endBehavioral;libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_ARITH.ALL;useIEEE.STD_LOGIC_UNSIGNED.ALL;----Uncommentthefollowinglibrarydeclarationifinstantiating----anyXilinxprimitivesinthiscode.--libraryUNISIM;--useUNISIM.VComponents.all;entitydivclkisport(clk:instd_logic;------50MHZclk400:outstd_logic;-------400KHZscanclk:outstd_Logic);enddivclk;architectureBehavioralofdivclkisbeginprocess(clk)variablecount:std_logic_vector(19downto0):=X00000;beginif(rising_edge(clk))thencount:=count+1;endif;clk400=count(2);scanclk=count(12);endprocess;endBehavioral;libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_ARITH.ALL;useIEEE.STD_LOGIC_UNSIGNED.ALL;----Uncommentthefollowinglibrarydeclarationifinstantiating----anyXilinxprimitivesinthiscode.--libraryUNISIM;--useUNISIM.VComponents.all;entitykey_boardisport(clr:instd_logic;clk400:instd_logic;--400KHZps2clk:instd_logic;ps2data:instd_logic;dataout:outstd_logic_vector(15downto0));endkey_board;architectureBehavioralofkey_boardissignalclk:std_logic:='0';signaldata:std_logic:='0';signalshift1,shift2:std_logic_vector(10downto0);signalps2c,ps2d:std_logic;beginps2c=ps2clk;ps2d=ps2data;dataout=shift1(8downto1)&shift2(8downto1);process(clk400,clr)variabletempclk:std_logic_vector(7downto0):=X00;variabletempdata:std_logic_vector(7downto0):=X00;beginif(clr='0')thentempclk:=X00;tempdata:=X00;clk='0';data='0';elseif(clk400'eventandclk400='1')thentempclk(0):=ps2c;tempclk(7downto1):=tempclk(6downto0);tempdata(0):=ps2d;tempdata(7downto1):=tempdata(6downto0);endif;endif;if(tempclk=11111111)thenclk='1';elseif(tempclk=00000000)thenclk='0';endif;endif;if(tempdata=11111111)thendata='1';elseif(tempdata=00000000)thendata='0';endif;endif;endprocess;process(clk,clr)beginif(clr='0')thenshift1=(others='0');shift2=(others='0');elseif(clk'eventandclk='0')thenshift1(10)=data;shift1(9downto0)=shift1(10downto1);shift2(10)=shift1(0);shift2(9downto0)=shift2(10downto1);--shift1(0)=data;--shift1(10downto1)=shift1(9downto0);--shift2(0)=shift1(10);--shift2(10downto1)=shift2(9downto0);endif;endif;endprocess;endBehavioral;libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_ARITH.ALL;useIEEE.STD_LOGIC_UNSIGNED.ALL;----Uncommentthefollowinglibrarydeclarationifinstantiating----anyXilinxprimitivesinthiscode.--libraryUNISIM;--useUNISIM.VComponents.all;entitydispisport(clr:instd_logic;scanclk:instd_logic;datain:instd_logic_vector(15downto0);a_to_g:outSTD_LOGIC_VECTOR(6downto0);sel:outSTD_LOGIC_VECTOR(3downto0);dp:outSTD_LOGIC);enddisp;architectureBehavioralofdispissignalS:std_logic_vector(1downto0);signaldigit:std_logic_vector(3downto0);begindp='1';process(scanclk)beginifrising_edge(scanclk)thenif(clr='0')thenS=00;elseS=S+1;endif;endif;endprocess;process(S)begincaseSiswhen00=digit=datain(3downto0);sel=0001;when01=digit=datain(7downto4);sel=0010;when10=digit=datain(11downto8);sel=0100;whenothers=digit=datain(15downto12);sel=1000;endcase;endprocess;process(digit)begin--casedigitis--whenX0=a_to_g=0000001;--whenX1=a_to_g=1001111;--whenX2=a_to_g=0010010;--whenX3=a_to_g=0000110;--whenX4=a_to_g=1001100;--whenX5=a_to_g=0100100;--whenX6=a_to_g=0100000;--whenX7=a_to_g=0001111;--whenX8=a_to_g=0000000;--whenX9=a_to_g=0000100;--whenXA=a_to_g=0001000;--whenXB=a_to_g=1100000;--whenXC=a_to_g=0110001;--whenXD=a_to_g=1000010;--whenXE=a_to_g=0110000;--whenXF=a_to_g=0111000;--whenothers=a_to_g=ZZZZZZZ;--endcase;casedigitiswhenX0=a_to_g=1111110;whenX1=a_to_g=0110000;whenX2=a_to_g=1101101;whenX3=a_to_g=1111001;whenX4=a_to_g=0110011;whenX5=a_to_g=1011011;whenX6=a_to_g=1011111;whenX7=a_to_g=1110000;whenX8=a_to_g=1111111;whenX9=a_to_g=1111011;whenXA=a_to_g=1110111;whenXB=a_to_g=0011111;whenXC=a_to_g=1001110;whenXD=a_to_g=0111101;whenXE=a_to_g=1001111;whenXF=a_to_g=1000111;whenothers=a_to_g=ZZZZZZZ;
本文标题:超完美VHDL数码管显示键值-PS2键盘控制实验
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