12 芯片验证(3学时)

1SoC芯片验证2Agenda•WhyVerification•VerificationAlternatives3WhatisDesignVerification?for(i=0;id;i=i+2){if(y3)p=p*3;elseq=q+r;}always@(posedgeclk)beginif(rst==1'b1)cnt=sv;elseif(cnt==2'b00)cnt=2'b01;elseif(cnt==2'b01)cnt=2'b10;elseif(cnt==2'b10)cnt=2'b11;elsecnt=sv;endbdeafbcdcg1g2g3g4g5g6g7g8g9Bottomline:tofixasmanybugsinyourdesignaspossibleVerificationtakes~70%ofresourcesintoday’sICdesign4•设计验证verification的目的是确认设计的功能正确性和性能（速度和功耗等）满足设计要求，贯穿于设计的整个过程RTLGDSIIGateDesignImplementationPhysicalImplementationRTLGDSIIGateDesignCreationDesignFlowFunctionalSpecification5WherearetheBugs?•Functionalspecification–systemorbehavior-leveldescriptions•Designcreation–Inconsistentwithspec–RTLcodingerror(typo,X,logicalerror)–Assumptionontheenvironment•Design/Physicalimplementation–Synthesistools–Manualoptimization6PercentageofTotalFlawsClocking5%Race5%Power4%Other9%Logical/Functional45%SlowPath13%Noise12%Yield7%7ImportanceofVerification•Morethanhalfofallchipsrequireoneormorere-spins,andthatfunctionalerrorswerefoundin74%ofthesere-spins.•Withincreasingchipcomplexity,thissituationcouldworsen.•Whocanaffordthatwith=1MDollarNREcost?8BugFixingCostinTime•Costoffixingabug/problemincreasesasdesignprogresses.–NeedverificationmethodatearlydesignstageBehavioralDesignRTLDesignGateLevelDesignDeviceProductionCostofFixingaProblem9Verificationvs.TestingDesignSpecificationDesignCreationDesignImplementationHigh-levelspecRTLdesignSynthesis/P&RChipManufactureICsVerificationTesting•Objectdesign•MethodologiesSimulationEmulationFormaltechniques•Objectchip•MethodologiesATPGFaultSimulationScan/BIST10Agenda•WhyVerification•VerificationAlternatives11VerificationAlternatives•Simulation•FPGAPrototyping•FormalVerification12VerificationMethodologiesSimulationFormalVerificationPrototypingBasicverificationtool13SoftwareSimulation•Dynamicverificationmethod•Bugsarefoundbyrunningthedesignimplementation.•Thoroughnessdependsonthetestvectorused.•Somepartsaretestedrepeatedlywhileotherpartsarenoteventested.a=1;#20b=1;$display(“statusis=%d”,c);...TestbenchDUVSomepartofthedesignistestedrepeatedly.Otherpartsarenoteventested.14SoftwareSimulation•Pros–Thedesignsizeislimitedonlybythecomputingresource.–SimulationcanbestartedassoonastheRTLdescriptionisfinished.–Set-upcostisminimal.•Cons–Slow(~kcycles/sec);Speedgapbetweenthespeedofsoftwaresimulationandrealsiliconwidens.(Simulationspeed=sizeofthecircuitsimulated/speedofthesimulationengine)–Thedesignerdoesnotexactlyknowhowmuchpercentageofthedesignhavebeentested.15RTL仿真•所使用的工具：VCSorModelsim•仿真步骤：–搭建RTL验证环境–编写RTL的testbench–编写ARM的测试代码–把ARM测试代码的二进制文件加载到RTL验证环境中的RAM中–开始运行arm测试程序–观察仿真波形，观察调试信息16搭建RTL验证环境•以DMAC模块的验证为例SOC芯片DMACSRAM1(CSA16*1)SRAM2(CSB8*1)SDRAM(CSE16*1)SRAM(CSF16*1)NAND(8*1)SSI模型17搭建RTL验证环境（续）•SoC芯片–ARM7TDMI–AMBA–DMAC模块–SSI控制模块–EMI–INTC•SoC芯片外接模型–SSI外设模型–SRAM模型–SDRAM模型–NAND模型18编写RTLtestbench19编写RTLtestbench•在初始化部分添加–系统复位信号–系统时钟信号激励•把SoC芯片的各个管脚连接好–暂无用的输入管脚置0或置1，暂无用的输出管脚可悬空–和功能验证相关的管脚必须对应连接好•每个片选上所接的存储器须按存储器的要求连接好各个信号线20编写arm测试代码•Arm初始化代码–汇编文件中的复位异常处理•中断处理–汇编文件中的IRQ异常处理–C文件中的中断处理•C文件中的初始化代码–在main.c文件中初始化PMC模块，设置系统时钟，打开模块的门控时钟等。21编写arm测试代码（续）•在main.c文件中编写各个功能验证代码•如验证存储器到存储器的数据传输–初始化DMA–设置存储器源地址和存储器目标地址–设置传输的数据大小–开始传输–中断服务程序•读取中断状态寄存器，看传输是完成了还是发生错误•如果是传输完成中断，则读出存储器目标地址的数据，看是否正确。22把ARM测试代码的二进制文件加载到RTL验证环境中的RAM中•Arm测试代码在ADS或RVDS软件开发环境中编译，生成axf文件•Axf需要转换成文本文件asc，一行8位或16位，视CSA片选所接存储器的宽度而定。–fromelf-vhx-8x1“ssi.axf-oasc•把asc加载到SoC的CSA片选所接的存储器中–在RTL的testbench中编写–$readmemh(asc,u_csa0.memory);23开始编译RTL代码并仿真•vcs-ffile_arm.f-lsim.log•其中file_arm.f文件中列出了所有的.v文件–Arm.v–Amba.v–Dmac.v–Ssi.v–Emi.v–Intc.v–Top.v–Ssi_model.v–Sdram.v–Sram.v–Nand.v–Test.v24开始运行arm测试程序•在testbench中所加的复位和时钟信号的激励下–arm在复位后从0x0地址取指令运行–0x0地址一般为片选CSA所接的存储器25观察仿真波形•普通、简单、基础而又易被忽视的信号！–CLK–RESET_N•但是无论在仿真还是测试中都是最重要的信号！！！•CLK•RESET_N26观察仿真波形（续）•看arm是否正常取指令运行–先取0x0地址中的跳转指令（e开头的指令），内容是否正确可参考asc文件中的第一行。–下一个取的地址就不是0x4，而是根据跳转指令而跳转到其它地址去取指令27观察仿真波形（续）•观察AMBA总线的信号是否正确•先看HTRANS信号–00：IDLE–01：BUSY–10：NONSEQ–11：SEQ28观察仿真波形（续）•HBUSREQ•HGRANTx•HSELx(Slaveselectsignal)•HLOCK•HTRANS[1:0]•HBURST[2:0]•HADDR[31:0]•HREADY(Slaveresponsesignal,transferdone.)•HRESP[1:0]•HWDATA[31:0]•HRDATA[31:0]•HWRITE29观察仿真波形（续）•看DMAC模块的接口信号波形•如果是存储器到外设的传输–看存储器的接口信号–看相应外设的接口信号•SSI30观察调试信息•如何把C代码中打印的调试信息打印到VCS仿真运行的控制台中？–在SoC芯片的顶层文件中例化Tube模块，作为一个AHBslave设备，设占用的地址为0x1100c000。–Tube模块接收往0x1100c000地址所写的字符并保存到log文件中。–在arm测试代码中的retarget.c文件实现print函数，print函数把要打印的调试信息发送到0x1100c000地址–则arm代码调用print函数，即可把调试信息打印到VCS仿真运行的控制台中。31VerificationAlternatives•Simulation•FPGAPrototyping•FormalVerification32Prototyping•Imitatingthefunctionofanothersystemtoachievethesameresultsastheimitatedsystem.•Usually,theprototypinghardwarecomprisesFPGA’s.•Morethan10000timesfasterthansimulation.SimulationPrototyping33Prototyping•Pros–Higherclockrate(upto~100Mcycles/sec)duetospecificdesignofprototypingboard.–Componentsaswellasthewiringcanbecustomizedforthecorrespondingapplication.–Canbecarriedalong.•Cons–Notflexiblefordesignchange–(Everynewprototyperequiresanewboardarchitecture./EvenasmallchangerequiresanewPCB.)34APrototypingExample35FPGA验证•