软FIFO在多DSP间通信中的应用(pdf 3)

2281,2133(1.7138002.935073.200233DSPFIFODSPVHDLApplicationofSoftwareFIFOinCommunicationofMulti-DSPLIUWei1,2,LEIYingjie1,NIMing3,CHAIXiaoli3(1.MissileInstitute,AirForceEngineeringUniversity,Xi’an713800;2.Unit93507,PLA;3.EastChinaInstituteofComputerTechnology,Shanghai200233)AbstractWithdevelopmentofdigitalinformation,therequirementsforcapabilityofdataprocessingincreasewithtimes,andmoreandmoredemandsforusingmulti-DSPstoworkinharmonizationcome.Asolutionforthehighspeedcommunicationsamongmulti-DSPsusingsoftwareFIFOisproposedwithavalidationbysimulation.Thesimulatedresultsshowthattheschemeisavailableineffect.KeywordsFIFODSPVHDLFPGAComputerEngineering3116Vol.311620058August200510003428(2005)16022803ATP303FIFOFIFOFIFOFIFO[2]FIFOFPGAFIFOXILINXIPFPGA1FIFOFIFOFIFORAM1FIFOFIFO2[3]1FIFO2FIFO//FIFO4(1)FIFO(RE)(WE)(EF)(FF)(HF)(AF)(AE)(2)FIFOFIFOFIFOUNCKLDCKOEFIFO(HF)(AF)(AE)(EF)(FF)(3)FIFOFIFORCLKWCLKFENWENOEFWFTFIFO(1976)[e-mail]/RAMFIFO32×32datain[31..0]WRCLKRDCLKWRENRDENRESERTdataout[31..0]FULLEMPTY229(4)FWFTFIFOFWFTFirstWordFallThroughFIFOFIFORCLKWCLKRENWENOEFirstWordFallThroughFIFOFWFTFIFOFWFTFIFOORIRFWFTFIFO2DSP(DSP)DSP16(1600MIPS)DSPDSPTITMS320C8xTMS320C6xADADSP2106x/ADSP2116xPowerPCMPC7400MFLOPSDSPDSPDSPPCI/OCPCIDSPDSPDSP3CPUCPUDSPDMARAMFIFODSPDMADSPRAMFIFODSPDSPDSP(C4X:DSPDSP)DSPDSP3FIFODSPRAMRAMA/DFIFOFIFOCPUCPUCPUCPUFIFOCPUFIFOFIFOFIFOCPUCPUTIC6000DSPFIFOEMIFFIFOTMS320C6000C67x32b167MHz(EMIF)C6000SRAMSDRAMFIFOEEPROMC6000FIFOFIFOFIFOC6000FIFOC6000FIFOC6000FIFOC6000FIFOC6000DSPEMIFFIFOFIFOFWFT(First-WordFall-Through)FIFO4C6201FIFO33FIFOFPGATMS320C6201DSP_0TMS320C6201DSP_1TMS320C6201DSP_2TMS320C6201DSP_3FIFO_0~1FIFO_0~3FIFO_0~2FIFO_1~2FIFO_1~3FIFO_2~3230FPGAFIFOFIFO232bFIFO632*32200MHz160Mb/s4FPGAFIFOFPGA(FieldProgrammableGateArray)ASICASICFPGAFPGAFPGADSPDSPFPGADSPVHDLVeryhighspeedintegratedcircuithardwaredescriptionlanguageAlterastratixcycloneVHDLDSPDSPQuartusII4.04VHDLFIFO1TO2:FIFO32TO32PORTMAP(wrclk=FIFO1TO2WE,rdreq=FIFO1TO2RREQ,rdclk=FIFO1TO2RE,wrreq=FIFO1TO2WREQ,data=FIFO1TO2DATAIN,rdempty=FIFO1TO2EMPTY,wrfull=FIFO1TO2FULL,q=FIFO1TO2DATAOUT)-------------------------------------PROCESS_FIFO_DSP1_TO_DSP2FIFO1TO2WRITE:PROCESS(FIFO1TO2WE)BEGINIF(FIFO1TO2WREQ='1'ANDFIFO1TO3FULL='0')THENFIFO1TO2DATAIN=DSP1DATA;ENDIF;ENDPROCESSFIFO1TO2WRITE;FIFO1TO2READ:PROCESS(FIFO1TO2RE)BEGINIF(FIFO1TO2RREQ='1'ANDFIFO1TO2EMPTY='0')THENDSP2DATA=FIFO1TO2DATAOUT;ELSEDSP2DATA=ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ;ENDIF;ENDPROCESSFIFO1TO2READ;41.DSP[M].,20002.FPGAFIFO[J].(),2003,35(2):383.FIFO[J].,2003,16(1):614.VHDL[M].,2003~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~(218)1ALOHAALOHA50.1%12846.22%546.22%1MelonS.TowardAGlobal“InternetofThings”.://~simplot/recherch/articles,20013,..:,1994