xilinx原语的使用方法

Xilinx13.4XilinxPrimitiveXilinxXilinxC++“cout”FPGALUTDRAMHDLCXilinxFPGAVerilogVirtex-4Xilinx10I/ORAM/ROMSlice/CLBG3.4.1DSP483-63-6DSP4818*183DSP4818481848Verilogmodulefpga_v4_dsp48(BCOUT,P,PCOUT,A,B,BCIN,C,CARRYIN,CARRYINSEL,CEA,CEB,CEC,CECARRYIN,CECINSUB,CECTRL,CEM,CEP,CLK,OPMODE,PCIN,RSTA,RSTB,RSTC,RSTCARRYIN,RSTM,RSTP,SUBTRACT);output[17:0]BCOUT;output[47:0]P,PCOUT;//input[17:0]A,B;//input[47:0]C,PCIN;input[1:0]CARRYINSEL;input[6:0]OPMODE;inputBCIN,CARRYIN,CEA,CEB,CEC,CECARRYIN,CECINSUB,CECTRL,CEM,CEP,CLK,RSTA,RSTB,RSTC,RSTCARRYIN,RSTM,RSTP,SUBTRACT;//DSP48DSP48#(.AREG(1),//NumberofpipelineregistersontheAinput,0,1or2.BREG(1),//NumberofpipelineregistersontheBinput,0,1or2.B_INPUT(DIRECT),//BinputDIRECTfromfabricorCASCADEfromanotherDSP48.CARRYINREG(1),//NumberofpipelineregistersfortheCARRYINinput,0or1.CARRYINSELREG(1),//NumberofpipelineregistersfortheCARRYINSEL,0or1.CREG(1),//NumberofpipelineregistersontheCinput,0or1.LEGACY_MODE(MULT18X18S),//Backwardcompatibility,NONE,MULT18X18orMULT18X18S.MREG(1),//Numberofmultiplierpipelineregisters,0or1.OPMODEREG(1),//NumberofpipelineregsitersonOPMODEinput,0or1.PREG(1),//NumberofpipelineregistersonthePoutput,0or1.SUBTRACTREG(1)//NumberofpipelineregistersontheSUBTRACTinput,0or1)fpga_v4_dsp48(.BCOUT(BCOUT),//18-bitBcascadeoutput.P(P),//48-bitproductoutput.PCOUT(PCOUT),//48-bitcascadeoutput.A(A),//18-bitAdatainput.B(B),//18-bitBdatainput.BCIN(BCIN),//18-bitBcascadeinput.C(C),//48-bitcascadeinput.CARRYIN(CARRYIN),//Carryinputsignal.CARRYINSEL(CARRYINSEL),//2-bitcarryinputselect.CEA(CEA),//Adataclockenableinput.CEB(CEB),//Bdataclockenableinput.CEC(CEC),//Cdataclockenableinput.CECARRYIN(CECARRYIN),//CARRYINclockenableinput.CECINSUB(CECINSUB),//CINSUBclockenableinput.CECTRL(CECTRL),//ClockEnableinputforCTRLregsiters.CEM(CEM),//ClockEnableinputformultiplierregsiters.CEP(CEP),//ClockEnableinputforPregsiters.CLK(CLK),//Clockinput.OPMODE(OPMODE),//7-bitoperationmodeinput.PCIN(PCIN),//48-bitPCINinput.RSTA(RSTA),//ResetinputforApipelineregisters.RSTB(RSTB),//ResetinputforBpipelineregisters.RSTC(RSTC),//ResetinputforCpipelineregisters.RSTCARRYIN(RSTCARRYIN),//ResetinputforCARRYINregisters.RSTCTRL(RSTCTRL),//ResetinputforCTRLregisters.RSTM(RSTM),//Resetinputformultiplierregisters.RSTP(RSTP),//ResetinputforPpipelineregisters.SUBTRACT(SUBTRACT)//SUBTRACTinput);endmodule3.4.2I/O3-73-71BUFGBUFGRTL3-28BUFGPLLDCM//BUFG:GlobalClockBuffer//XilinxHDLISE9.1BUFGBUFG_inst(.O(O),//.I(I)///);//BUFG_insRTL3-323-32RTL2.BUFMUXBUFMUXI0I1BUFMUX1RTLMSI0I1MBUFMUXBUFMUX1BUFMUX1SI1I0BUFMUX//BUFGMUX:21GlobalClockBuffer2-to-1MUX//Virtex-II/II-Pro/4/5,Spartan-3/3E/3A//XilinxHDLISE9.1BUFGMUXBUFGMUX_inst(.O(O),//.I0(I0),//0.I1(I1),//1.S(S)//);//BUFGMUX_instBUFMUX1RTL3-333-33RTL3.BUFIOBUFIOI/ORTLBUFIOI/OBUFIOI/OBUFRBUFIOI/OCLBRAMBUFIO//BUFIO:I/OLocalClockBuffer//Virtex-4/5//XilinxHDLISE9.1BUFIOBUFIO_inst(.O(O),//I/O.I(I)//I/O);//BUFIORTL3-343-34I/ORTL4.BUFRBUFRI/ORTLBUFRBUFIOBUFR3I/OBUFIOBUFRBUFR18BUFRBUFIO//BUFR:I/ORegionalClockBuffer//Virtex-4/5//XilinxHDLISE9.1BUFR#(.BUFR_DIVIDE(BYPASS),//BYPASS,1,2,3,4,5,6,7,8.SIM_DEVICE(VIRTEX4)//,VIRTEX4VIRTEX5)BUFR_inst(.O(O),//.CE(CE),//.CLR(CLR),//.I(I)//);//BUFRBUFIOBUFRVirtex-4RTL3-353-35I/ORTL5.DCM_BASEDCM_BASEFPGADCM_ADVDCM_PSDCMRTL3-83-8DCM_BASEXilinxIPWizardVerilog//DCM_BASE:BaseDigitalClockManagerCircuit//Virtex-4/5//XilinxHDLISE9.1DCM_BASE#(.CLKDV_DIVIDE(2.0),//CLKDV:1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5//7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0or16.0.CLKFX_DIVIDE(1),//Canbeanyintegerfrom1to32//CLKFX132.CLKFX_MULTIPLY(4),//CLKFX232.CLKIN_DIVIDE_BY_2(FALSE),//2TRUE/FALSE.CLKIN_PERIOD(10.0),//ns1.25~1000.00.CLKOUT_PHASE_SHIFT(NONE),//NONEFIXED.CLK_FEEDBACK(1X),//NONE1X2XCLK0.DCM_PERFORMANCE_MODE(MAX_SPEED),//DCMMAX_SPEEDMAX_RANGE.DESKEW_ADJUST(SYSTEM_SYNCHRONOUS),//0~15.DFS_FREQUENCY_MODE(LOW),//LOWHIGH.DLL_FREQUENCY_MODE(LOW),//DLLLOWHIGHHIGH_SER.DUTY_CYCLE_CORRECTION(TRUE),//TRUEFALSE.FACTORY_JF(16'hf0f0),//16JF.PHASE_SHIFT(0),//-255~1023.STARTUP_WAIT(FALSE)//DCMDONETRUE/FALSE)DCM_BASE_inst(.CLK0(CLK0),//0DCM.CLK180(CLK180),//180DCM.CLK270(CLK270),//270DCM.CLK2X(CLK2X),//DCM2.CLK2X180(CLK2X180),//180DCM2.CLK90(CLK90),//90DCM.CLKDV(CLKDV),//DCMCLKDV_DIVIDE.CLKFX(CLKFX),//DCM(M/D).CLKFX180(CLKFX180),//180DCM.LOCKED(LOCKED),//DCM.CLKFB(CLKFB),//DCM.CLKIN(CLKIN),//DCM.RST(RST)//DCM);//DCM_BASEDCMRTL3-363-36DCMRTL3.4.3FPGAJTAG63-93-9BSCAN_VIRTEX41BSCAN_VIRTEX4JTAGUSER1/2/3/4BSCAN_VIRTEX4TCKTMSTDIJTAGTDOPCJTAGBSCAN_VIRTEX4CAPTURE1JTAGCAPTURE-DRDRCK1JTAGTCKJTAGJTAGSHIFT-DRRESET1JTAGTEST-LOGIC-RESETSEL1USER1JTAGUPDATE-IRSHIFT1JTAGSHIFT-DRTDI1JTAGTDIUPDATE1USER1USER2JTAGUPDATE-DRTDO1JTAGTDOVirtex-44BSCAN_VIRTEX4JTAG_CHAIN141BSCAN_VIRTEX4//BSCAN_VIRETX4:JTAGBoundaryScanprimitiveforconnectinginternallogictoJTAGinterface.//Virtex-4/5//XilinxHDLISE9.1BSCAN_VIRETX4#(.JTAG_CHAIN(1)//JTAG1,2,3,4)BSCAN_VIRETX4_inst(.CAPTURE(CAPTURE),//TAP.DRCK(DRCK),//.RESET(RESET),//TAP.SEL(SEL),//.SHIFT(SHIFT),//TAP.TDI(TDI),//TAPTDI.UPDATE(UPDATE),//TAPUPDATE.TDO(TDO)//);//BSCAN_VIR