DS2001 roadshow

CadenceDesignSystems,Inc.Cadence’sSolutionforHigh-SpeedDesign‹#›confidentialAgendaWhatisHigh-SpeedDesign?IdealHigh-SpeedDesignProcessIntroductiontoSPECCTRAQuestPowerIntegritySPECCTRAQuestDemonstration‹#›confidentialRTheDayof“High-Speed”HasCome“Pc-boarddesigners,meanwhile,wereretoolingin1999forhigh-speeddesign.Signalintegrity,onceconfinedtohigh-endboards,hasbecomeeverybody’sproblem…”RichardGoering,commentingonwhythePCBlayoutmarketgrew20%whiletheIClayoutmarketshrunk30%,inEETimes4/10/2000page70‹#›confidentialWelcomeNetworking!HammerheadNetworksR‹#›confidentialAgendaWhatisHigh-SpeedDesign?IdealHigh-SpeedDesignProcessSPECCTRAQuestDemonstrationIntroductiontoSPECCTRAQuestPowerIntegrityNOW‹#›confidentialWhatis“High-Speed”?Huh?‹#›confidentialQuestion:Whichisa“High-Speed”Problem?‹#›confidentialAnswer:TheyBOTHAre!!‹#›confidentialDefinitionofHigh-SpeedAnetcanbeconsidered‘High-Speed’whenyouhavetodosomethingotherthansimplyconnectit.‹#›confidentialHigh-SpeedDesignInvolves2ThingsNetsthatareunderstood,andmustbeconstrainedNetsthatmustbeanalyzedtobeunderstood,andthenconstrained‹#›confidentialNetsthatareunderstood,andmustbeconstrainedNetsthatmustbeanalyzedtobeunderstood,andthenconstrainedSDRAMDIMMLayoutMODELSDatasheetsFront-sideBusSimulation‹#›confidentialMostToolsForceYoutoChooseAnalyzeConstrainHmm...‹#›confidentialButforHigh-SpeedYouNeedBOTHAllinONEintegrated&interactiveenvironment!Analyze&ConstrainLet’sGo!‹#›confidential‹#›confidentialSPECCTRAQuest:IntegratedConstraint&AnalysisModelDevelopment&VerificationTopologyEntry&FloorplanningConstraintDrivenLayoutAnalyzeConstrainSPECCTRAQuesthelpsyoumanagetheprocessofHigh-SpeedPCBdevelopmentthroughbothSimulationAnalysis&Constraint-DrivenLayouttasksACompleteSolution!Pre-RouteSol’n-SpaceAnalysisPostRouteAnalysisVerificationVerification‹#›confidentialExpandingExistingProcessPhysicalModelCreationOutline/Floorplan/RoomDef/SchematicModelCreationSchematicCreationSCHEMATICLAYOUTToFinalVerificationnetlistSICleanRouteconstraintsBack-AnnotateRe-useTopologyFilesTopologyFilesTopologyFilesDeriveConstraintsElectricalModelCreationHIGH-SPEEDyesnoPost-RouteAnalysisrules/criticals/placement/ACsOK?“IP”LibraryPCBRouting‹#›confidentialAgendaWhatisHigh-SpeedDesign?IdealHigh-SpeedDesignProcessSPECCTRAQuestDemonstrationIntroductiontoSPECCTRAQuestPowerIntegrityNOW‹#›confidentialIdealHigh-SpeedDesignFlowModelDevelopment&VerificationTopologyEntry&FloorplanningConstraintDrivenLayoutAnalyzeConstrainDevelopmentProcessFlowPre-RouteSol’n-SpaceAnalysisPostRouteAnalysisVerificationVerificationModelDevelopment&Verification‹#›confidentialNeedFlexibleDeviceModelingLanguage(DML)Today’smodelscomeinmanystylesandformatsCadenceDMLcanmodelallformatsANDadvancedbehaviors(forexample,Merced/Itanium)QuadModelsVersion2.1Version3.2IBISPackage,TransmissionLine,Connector,CableModelsSPICEModelsEBDModelsCadenceDMLcan’tdo“M”elementtoday‹#›confidentialIdealHigh-SpeedDesignFlowModelDevelopment&VerificationTopologyEntry&FloorplanningConstraintDrivenLayoutAnalyzeConstrainDevelopmentProcessFlowPre-RouteSol’n-SpaceAnalysisPostRouteAnalysisVerificationVerificationPre-RouteSol’n-SpaceAnalysis‹#›confidentialPre-RouteSolutionSpaceAnalysisExhaustive“pre-layout”analysisofmanufacturinganddesignvariancesUsedtodefinetopologies,routingrulesandterminationstrategiesCrosstalkanddatapatterndependenciesmaybetakenintoconsiderationSwept-parameteranalysisisusedextensivelytocoverallcombinationsofconditionsNeedflexibilitytodefineanykindofsimulationandanykindofmeasurementcriteria‹#›confidentialOutputofpre-layoutprocessisanelectronicconstraintfilethatcanbeusedtoguidethelayoutprocessAnalyzeDeriveandSave“SolutionSpace”Constrain‹#›confidentialIdealHigh-SpeedDesignFlowModelDevelopment&VerificationTopologyEntry&FloorplanningConstraintDrivenLayoutAnalyzeConstrainDevelopmentProcessFlowPre-RouteSol’n-SpaceAnalysisPostRouteAnalysisVerificationVerificationTopologyEntry&Floorplanning‹#›confidentialHigh-SpeedPCBDesignNowRequiresBothElectronicInputstoFloorplanning&RoutingTopologyFilesFinalNetlistELECTRICALLOGICALPCBRoutingPHYSICALTopologyFilesFinalNetlistELECTRICALLOGICALPCBRoutingPCBRoutingPHYSICAL‹#›confidentialTopologyEntryandFloorplanningDesignrulesderivedfromsolutionspaceanalysisguidetheplacementprocessConstraintManagerspreadsheetsplaysakeyroleinguiding/evaluatingcomponentplacementMargincolumnsshowdifferencebetweenconstraintanddesignvalue–Fastfeedback–Color-codedstatus‹#›confidentialIdealHigh-SpeedDesignFlowModelDevelopment&VerificationTopologyEntry&FloorplanningConstraintDrivenLayoutAnalyzeConstrainDevelopmentProcessFlowPre-RouteSol’n-SpaceAnalysisPostRouteAnalysisVerificationVerificationConstraintDrivenLayout‹#›confidentialConceptHDLCaptureSPECCTRAQuestExplorationSPECCTRAQuestFloorplanningAllegro/APDLayoutConstraintManagerCaptureExplorationFloorplanningLayoutGUIGUIGUIGUIConstraintsConstraintsConstraintsConstraints???ePlanner/QUADSPICEHyperLynxViewDrawICXDesignBoardStationPADSVeriBestArchitectePlannerConstraintManagementToday‹#›confidentialPSD14.0