VHDL_语言入门

–Simulation–Synthesis–OverviewoflanguagenDesignUnits–Entity–Architecture–Configurations–Packages(Libraries)nArchitectureModelingFundamentals–Signals–Processes•SequentialStatements–ProcessStatement–InferringLogicnModelApplication–StateMachineCodingnHierarchicalDesigning–Overview–StructuralModeling–ApplicationofLPM’s(VeryHighSpeedIntegratedCircuit)HardwareDescriptionLanguage(DOD)fundedaprojecttocreateastandardhardwaredescriptionlanguageundertheVeryHighSpeedIntegratedCircuit(VHSIC)program.n1987-theInstituteofElectricalandElectronicsEngineers(IEEE)ratifiedasIEEEStandard1076.n1993-theVHDLlanguagewasrevisedandupdatedtoIEEE1076‘93.(j):=shft(j);ENDLOOP;output1=shftAFTER5nsnOnlythefunctionalityofthecircuit,nostructurenNospecifichardwareintentnForthepurposeofsynthesis,aswellassimulation(RTL)-Atypeofbehavioralmodeling,forthepurposeofsynthesis.–Hardwareisimpliedorinferred–SynthesizablenSynthesis-TranslatingHDLtoacircuitandthenoptimizingtherepresentedcircuitnRTLSynthesis-TheprocessoftranslatingaRTLmodelofhardwareintoanoptimizedtechnologyspecificgatelevelimplementation(a,b,c,d,sel)begincase(sel)iswhen“00”=mux_out=a;when“01”=mux_out=b;when“10”=mux_out=c;when“11”=mux_out=d;endcase;adadTranslationOptimizationadsel2binferredmux_outc–“TellmehowyourcircuitshouldbehaveandIwillgiveyouhardwarethatdoesthejob.”nVerilog–SimilartoVHDLnABEL,PALASM,AHDL–“TellmewhathardwareyouwantandIwillgiveittoyou”–“Givemeacircuitwhoseoutputonlychangeswhenthereisalow-to-hightransitiononaparticularinput.Whenthetransitionhappens,maketheoutputequaltotheinputuntilthenexttransition.”–Result:VHDLSynthesisprovidesapositiveedge-triggeredflipflopnABEL,PALASM,AHDL–“GivemeaD-typeflipflop.”–Result:ABEL,PALASM,AHDLsynthesisprovidesaD-typeflipflop.Thesenseoftheclockdependsonthesynthesistool.:–Synthesis–SimulationnTheVHDLLanguageismadeupofreservedkeywords.nThelanguageis,forthemostpart,NOTcasesensitive.nVHDLstatementsareterminatedwitha;nVHDLiswhitespaceinsensitive.Usedforreadability.nCommentsinVHDLbeginwith“--”toeolnVHDLmodelscanbewritten:–Behavioral–Structural–Mixed–Entity•Usedtodefineexternalviewofamodel.i.e.symbol–Architecture•Usedtodefinethefunctionofthemodel.i.e.schematic–Configuration•UsedtoassociateanArchitecturewithanEntity–Package•CollectionofinformationthatcanbereferencedbyVHDLmodels.I.e.Library•ConsistoftwopartsPackageDeclarationandPackageBody.(1076-1987version)ENDENTITYentity_name;(1076-1993version)nAnalogy:Symbolnentity_namecanbeanyalpha/numericalname–Note:MAX+PLUSIIrequiresthattheentity_nameandfile_namebethesame.nGenericDeclarations–Usedtopassinformationintoamodel.–MAX+PLUSIIplacesomerestrictionontheuseofGenerics.nPortDeclarations–Usedtodescribetheinputsandoutputsi.e.pins(constanttplh,tphl:time:=5ns--Noteconstantisassumedandisnotrequiredtphz,tplz:time:=3ns;default_value:integer:=1;cnt_dir:string:=“up”);PortDeclarationsENDentity_name;(1076-1987version)ENDENTITYentity_name;(1076-1993version):classobject_name:modetype;•class:whatcanbedonetoanobject•Object_name:iden