VHDL语言的UART串行接口芯片设计程序清单

VHDL语言的UART串行接口芯片设计程序清单附录1数据接收据器的VHDL语言描述清单LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;useieee.std_logic_unsigned.all;useieee.std_logic_arith.all;useieee.std_logic_signed.all;ENTITYUART_receiverISPORT(RxD,Bclkx8,sysclk,reset,RDRF:INSTD_LOGIC;RDR:OUTSTD_LOGIC_VECTOR(7DOWNTO0);setRDRF,setOE,setFE:OUTSTD_lOGIC);ENDUART_receiver;ARCHITECTURErtlOFUART_receiverISTYPEstateTYPEIS(R_WAiT,START_DETECTED,R_DATA);SIGNALstate,nextstate:stateTYPE;SIGNALRSR:STD_LOGIC_VECTOR(7DOWNTO0);SIGNALcnt1:INTEGERRANGE0TO7;SIGNALcnt2:INTEGERRANGE0TO8;signalclr1,clr2:std_logic;SIGNALinc1,inc2,shftRSR,loadRDR:STD_LOGIC;SIGNALBclkx8_Dlayed,Bclkx8_rising:STD_LOGIC;BEGINBclkX8_rising=Bclkx8AND(NOTBclkx8_dlayed);R_control:PROCESS(state,RxD,RDRF,cnt1,cnt2,BclkX8_rising)BEGIN--inc1='0';inc2='0';--clr1='0';clr2='0';shftRSR='0';loadRDR='0';setRDRF='0';setOE='0';setFE='0';CASEstateISWHENR_WAIT=IF(Rxd='0')THENnextstate=START_DETECTED;ELSEnextstate=R_WAIT;ENDIF;WHENSTART_DETECTED=IF(Bclkx8_rising='0')THENnextstate=START_DETECTED;ELSIF(RxD='1')THENclr1='1';nextstate=R_WAIT;ELSIF(cnt1=3)THENclr1='1';nextstate=R_WAIT;ELSEinc1='1';nextstate=START_DETECTED;ENDIF;WHENR_DATA=IF(Bclkx8_rising='0')THENnextstate=R_DATA;ELSEinc1='1';IF(cnt1/=7)THENnextstate=R_DATA;ELSIF(cnt2/=8)THENshftRSR='1';inc2='1';clr1='1';nextstate=R_DATA;ELSENextstate=R_WAIT;setRDRF='1';clr1='1';clr2='1';IF(RDRF='1')THENsetOE='1';ELSIF(RXD='0')THENsetFE='1';ELSEloadRDR='1';ENDIF;ENDIF;ENDIF;ENDCASE;ENDPROCESS;R_update:PROCESS(sysclk,reset)BEGINIF(reset='0')THENstate=R_WAIT;BclkX8_Dlayed='0';cnt1=0;cnt2=0;ELSIF(syscLk'EVENTANDsysclk='1')THENstate=nextstate;IF(clr1='1')THENcnt1=0;ELSIF(inc1='1')THENcnt1=cnt1+1;ENDIF;IF(clr2='1')THENcnt2=0;ELSIF(inc2='1')THENcnt2=cnt2+1;ENDIF;IF(shftRSR='1')THENRSR=RxD&RsR(7DOWNTO1);ENDIF;IF(loadRDR='1')THENRDR=RSR;ENDIF;BclkX8_Dlayed=BclkX8;ENDIF;ENDPROCESS;ENDrtl;附录2数据发送器的VHDL语言描述清单LIBRARYIEEE;USEIEEE．STD_LOGIC_1164．ALL;ENTITYUART_transmitterISPORT(Bclk，sysclk，reset，TDRE，loadTDR：INSTD_LOGIC;DBUS：INSTD_LOGIC_VECTOR(7DOWNTO0);setTDRE，TxD：OUTSTD_LOGIC);ENDUART_transmitter;ARCHITECTURErtlOFUART_transmitterISTYPEstateTYPEIS(T_WAlT，SYNCH，T—DATA);SIGNALstate，nextstate：stateTYPE；SIGNALTDR：STD_LOGIC__VECTOR(7DOWNTO0)：SIGNALTSR：STD_LOGIC_VECTOR(8DOWNTO0);SIGNALBcnt：INTEGERRANGE0TO9;SIGNALinc，clr，loadTSR，shftTSR，start：STD-LOGIC;SIGNALBclk_rising，Bclk_Dlayed：STD_LOGIC;BEGINTxD=TSR(0)：setTDRE=loadTSR；Bclk_rising=BclkAND(N0TBclk_Dlayed);T_control:PROCESS(state，TDRE，Bcnt，Bclk_rising)BEGINinc=’0’：clr='0'；loadTSR=’0’；shftTSR='0';start='0';CASEstateISWHENT_WAIT=IF(TDRE=’0’)THENloadTSR=’1’nextstate=SYNCH;ELSEnextstate=T_WAIT;ENDlF;WHENSYNCH=IF(Bclk_rising=’1’)THENstart=’1’;nextstate=T_DATA;ELSEnextState=SYNCH;ENDIF;WHENT_DATA=IF(Bclk_rising='0')THENnextstate=T_DATA;ELSIF(Bcnt／=9)THENshftTSR='l';iucl;nextstate=T_DATA;ELSEclr=’1’;nextstate=T_WAIT;ENDIF;ENDCASE;ENDPROCESS;T_updale;PROCESS(sysclk,reset)BEGINIF(reset=’0’)THENTSR=”111111111”;state=T_WAIT,Bcnt=0;Bclk_dlayed=’0’;ELSIF(sysclk’EVENTANDsysclk=’1’)THENState=nextstate;IF(clr=’l’)THENBcnt=0;ELSIF(inc=’l')THENBcnt=Bcnt+1;ENDIF;IF（loadTDR=T)THENTDR=DBUS;ENDIF;IF(loadTSR=‘1’)THENTSR=TDR&’1’;ELSIF(START='I')THENTSR(0)=‘0’;ELSIF(shffrSR='1')THENTSR='I，&TSR(8DOWNT01);ENDIF;Bclk_Dlayed=Bclk;ENDIF;IF(loadTDR=’1’)THENTDR=DBUS;ENDIF;IF(loadTSR=’1’)THERTSR=TDR&’1’;ELSEIF(START=’1’)THENTSR(0),=’0’;ELSEIF(shiftTSR=’1’)THENTSR=’1’&TSR(8DOWNTO1);ENDIF;Bclk_Dlayed=Bclk;ENDIF;ENDPROCESS;ENDrtl;附录3波特率发生器的VHDL语言描述清单LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGlC_UNSIGNED.ALL;ENTITYUART_clkdivISPOPT(sysclk:iNSTD_LOGlC;sel:INSTD_LOGIC_VECTOR(2DOWNTO0);BclkX8:BUFFERSTD_LOGIC;Bclk:OUTSTD_LOGIC);ENDUART_clkdiv;ARCHITECTURErtlOFUART_clkdivISSIGNALdivl:STD_LOGIC_VECTOR(3DOWNTO0):=0000;SIGNALdiv2:STD_LOGIC_VECTOR(7DOWNTO0):=00000000;SIGNALdiv3:STD_LOGIC_VECTOR(2DOWNTO0)=000;SIGNALclkdivl3:STD_LOGIC;BEGINdiv_13:prOCESS(syselk)BEGINIF(sysclk'EVENTANDsysclk='1')THENIF(div1=1100)THENdiv1=0000;ELSEdiv1=divl+1;ENDIF;ENDIF;ENDPROCeSS;BEGINIF(clkdivl3'VENTANDclkdivl3='1')THENdiv2=div2+l;ENDIF;ENDPROCESS;clkdiv13=div1(3);div_pro:PROCESS(clkdiv13);BEGINIF(clkdiv13'EVENTANDclkdiv13='1')THENdiv2=div2=1;ENDIF;ENDPROCESS;BclkX8=div2(CONV_INTEGER(sel))；--selectbaudratediv_8:pROCESS(BclkX8)BEGINIF(BclkX8'EVENTANDBcLkXS='1')THENdiv3=dlv3+1;ENDIF;ENDPROCESS;bclk=div3(2);ENDrtl;LIBRARYIEEE;USEIEEE.STD_LOGIC_11164.ALL;USEIEEE.STD_LOGlC_UNSIGNED.ALL;ENTITYUART_clkdivISPOPT(sysclk：INSTD_LOGlC;sel:INSTD_LOGIC_VECTOR(2DOWNTO0);BclkX8：BUFFERSTD_LOGIC;Bclk:OUTSTD_LOGIC);ENDUART_clkdiv;ARCHITECTURErtlOFUART_clkdivISSIGNALdivl:STD_LOGIC_VECTOR(3DOWNTO0)：=”0000”;--divideby13counterSIGNALdiv2：STD_LOGIC_VECTOR(7DOWNTO0)：=”00000000”;--divideby256counterSIGNALdiv3:STD_LOGIC_VECTOR(2DOWNTO0)=”000”;--Divideby8counterSIGNALclkdivl3:STD_LOGIC;BEGINdiv_13：PROCESS(syselk)BBGINIF(sysclk’EVENTANDsysclk=’1’)THENIF(div1=1100)THENdiv1=0000;ELSEdiv1=divl+1;ENDIF;ENDIF;ENDPROCSS（clkdivl3）BEGI