7024 Programming Guide_RegTab1.4

ChrontelCH7023/CH7024ProgrammingGuideRev1.405/12/20061CH7023/CH7024TVENCODERPROGRAMMINGGUIDEInformationpresentedinthisdocumentisrelevanttoChronteldrivermodulesoftware,andChrontelTV-Outchipsetproducts.ItmaybeonlyusedforChrontelsoftwaredevelopmentaid.Itmaynotbeusedforanyotherpurpose.Chrontelandauthorofthisdocumentarenotliableformisuseofinformationcontainedherein.Chrontelandauthorofdocumentarenotliableforerrorsfoundherein.InformationcontainedhereinmaynotbeusedwithinlifesupportsystemsornuclearfacilityapplicationswithoutthespecificwrittenconsentofChrontel.Donotdistributethisdocumenttonon-designatedunauthorizedpartiesinanyformwithoutthespecificwrittenconsentofChrontel.Donotreadanddestroythisdocumentifyouarenotdesignatedrecipient.Informationcontainedhereinissubjecttochangewithorwithoutnotice.CommunicatewithChrontelSoftwareandSystemsEngineeringDepartmentforup-to-datechanges.Revision1.4May12,2006PreparedBy:LiFeng&PuYangReviewedBy:EricTzouChrontelChrontelCH7023/CH7024ProgrammingGuideRev1.405/12/20062TableofContentsChipIdentification.….…………………………………………………………………………3SystemConfiguration…………………………………………………………………………3SyncControl……………………………..………………………………………………3ClockSetting….……………………..……………………...…………………………...4DACSetting………………………………..…………………………………………….5UsingUtility………………………………………………………………………………..……7Sub-carrierGeneration….…………………………………………………………………..20Timing………………………………………………………………………….……………….21InputTiming………………………………………………………………………..…..21InputDataFormat……………………………………………………………………..23Scaling……………………………………………………………………….…………24VideoOutputFormat………………………………………………………………………...25PowerManagement&ConnectionDetection……………………………..…………….26PowerManagement.…………………………………………………………………..26ConnectionDetection………………………………………………………………….26Feature…………………...…………………………………………………………………….28ControlRegisters……………………………………………………………………...28Position………………………………………………….………….…………………..29BandwidthControlandTVFilter.……………………….…………..…..…………..30ProgrammingSequence….………………………………………………………………...32AppendixAProgrammingIDF=5(YCbCr4:2:2)..………..………………..…………...33AppendixBTestMode……………………………....………..………………..…………...35RevisionHistory……….….………………………………………………………………….36ChrontelCH7023/CH7024ProgrammingGuideRev1.405/12/20063CHIPIDENTIFICATIONTheCH7023/4isadevicetargetinghandheldandsimilarsystemswhichacceptsadigitalinputsignal,andencodesandtransmitsdatathrough10-bitDACs.ThedeviceisabletoencodethevideosignalsandgeneratesynchronizationsignalsforNTSCandPALstandards.ThedeviceacceptsdifferentdataformatsincludingRGBandYCrCb(e.g.RGB565,RGB666,RGB888,ITU656likeYCrCb,etc.).TheonlydifferencefromCH7023andCH7024isCH7023hasMacrovisioncopyprotectioncapabilityandCH7024doesnot.FollowingthestepsbelowtoidentifyCH7023/CH7024chip.Step1:Readthevalueofregister0x00;Ifvalueis0x45,CH7023/CH7024ispresent.Othervalue,noneofCH7023/CH7024ispresent;Step2:Write‘1’tobit1ofregister0x40(set0x40[1]=1)andreadback;Ifthebitis‘0’,thechippresentisCH7024;Elsethebitis‘1’,thechippresentisCH7023.Note:Individualbit(s)ofaregisterisenclosedbysquarebrackets.Forexample,bit1ofregister0x40iswrittenas0x40[1],and0x40[1:0]meansbits1and0ofregister0x40.SYSTEMCONFIGURATION•SYNCControlRegister0Ehshouldbeconfiguredtocontrolsyncinformation.Address:0Eh76543210SYMBOL:DESHPOVPOSYOTYPE:R/WR/WR/WR/WR/WR/WR/WR/WDEFAULT00001100DESDES(0x0E[6])definestheinputsynctype.WhenDESis‘1’,inputsyncisencodedinsidetheinputdata;whenDESis‘0’,inputsyncisindependentwithinputdata.ThisbitshouldbesetwhenthesourceisYCbCr4:2:2.HPO,VPOHPO(0x0E[3])definesthepolarityofhorizontalsync.WhenHPOis‘1’,thepolarityispositive;otherwiseisnegative.VPO(0x0E[2])definesthepolarityofverticalsync.WhenVPOis‘1’,thepolarityispositive;otherwiseisnegative.ChrontelCH7023/CH7024ProgrammingGuideRev1.405/12/20064SYOSYO(0x0E[1])definesthedirectionofsync.WhenSYOis‘0’,inputsync;otherwiseoutputsync.•CLOCKSETTINGPOUTENRegister0x0Ebit7isindictorformasterandslavemodeselection.Address:0Eh76543210SYMBOL:POUTENTYPE:R/WR/WR/WR/WR/WR/WR/WR/WDEFAULT00001100POUTEN(0x0E[7])enablesthemastermodePCLKoutputthroughPOUTpin.WhenPOUTENissetthechipworksonmastermodeotherwiseonslavemode.OnmastermodetheusershouldprovidethevalueofPOUTfrequencytocalculatethevaluesofPLL1N1,PLL2N2andA(SeePLLSetting).XCHAddress:0Fh76543210SYMBOL:XCHTYPE:R/WR/WR/WR/WR/WR/WR/WR/WDEFAULT00000000XCH(bit7)isanauxiliarybittohelplatchinputdatacorrectly.WhenMULTIis‘1’orIDFequal‘5’,thisbitshouldbe‘1’,otherwiseshouldbe‘0’.CrystalRegisterAddress:0Bh76543210SYMBOL:XTALSELReservedReservedReservedXTAL[3]XTAL[2]XTAL[1]XTAL[0]TYPE:R/WR/WR/WR/WR/WR/WR/WR/WDEFAULT00000100XTALSEL(0x0B[7]):whetherthecrystalfrequencyispredefinedornot.Whenthecrystalfrequencyispredefined,someregisters,suchasSCFREQ,willbecalculatedinsidethechiptosaveprogrammingeffort.ChrontelCH7023/CH7024ProgrammingGuideRev1.405/12/200650:Usingpredefinedvalue.1:Usingothervalue.WhenXTALSELsettopredefinedvalue,XTAL[3:0](bits3-0)havetoprogramfollowbythetablebelow:0:3.6864MHz,1:3.579545MHz,2:4MHz,3:12MHz,4:13MHz,5:13.5MHz,6:14.318MHz,7:14.7456MHz,8:16MHz,9:18.432MHz,10:20MHz,11:26MHz,12:27MHz,13:32MHz,14:40MHz,