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BehavioralModelandSimulationofAnalogCircuitsUsingVerilog-AZHUZhang-ming,ZHANGChun-peng,YANGYin-tang,FUYong-chao(MicroelectronicsInstitute,XidianUniversity,Xi'an710071,China)Abstract: ThecharacteristicandstructureofVerilog-AHDLareanalyzed.Consideredthetrade-offbetweensimulationspeedandaccuracy,thebehavioralmodelofanalogswitch,bandgapvoltagereferenceandoperationalamplifierareim-plementedusingVerilog-A.Basedonthecharacteristicofdigital-to-analogconverter,themodelofparametertestbenchand8-bitDACareimplementedusingVerilog-A.allbehavioralmodelareverifiedbythesimulationtoolofCadenceSpec-tre.Keywords: Verilog-A;Behavioral;Model;SimulationEEACC: 1130BVerilog-A①朱樟明,张春朋,杨银堂,付永朝(,710071):Verilog-A,,、Verilog-A。(DAC),Verilog-ADAC,8DAC。CadenceSpectre。:Verilog-A;;;:TN402 :A :1005-9490(2003)04-0396-04 ,(SOC)。SOCIP,、(DSP)、/(ADC)、/(DAC)、、(RF),,IP,[1],SOC。SOCIPSOC、、,。SOC,IPSpice。,,264200312 ChineseJournalofElectronDevices Vol.26,No.4Dec.2003①:2003-06-06:863(2002AA1Z1210):(1978-),,,、 ADC/DACSOC,zmyh@263.net; (1979-),,,、 DAC; (1962-),,、、,、 ; (1978-),,,、 DAC.。Verilog-A,,、IP。IP,SOC,ADC。1 Verilog-A Verilog-A、[2-3],,、、。Spice,Verilog-A,、,。-1Verilog-A。1 Verilog-Amodulebandgap(〉);〈〉〈〉〈〉analogbegin 〈〉end module ,Verilog-A,limexp()、idt()、ddt()delay()。,,、、(APLL)、(VCO)、MOS、、/(DAC)/(ADC),SOCIP。IPVeril-og-ASpectre,SOC,IP。2 Verilog-A2.1,,CMOS、。,CMOS、/IP。:、、。,Verilog-A,。Verilog-A,,“transition”,。RC,,。CadenceSpectre,、,。,,。Verilog-A,,V(out,in)+0.0(1)2.2 1CMOS,,Q1、Q2、Q3NP(BJT)。I1R1+VEB1=VEB2(2)VEB=VTlnIIS(3)(2)(3),I1=VEB2-VEB1R1=VTR1lnIS1IS2(4)VREF=R2R1VTlnIS1IS2+VEB3(5),Verilog-A:`include“std.va”`include“const.va”modulebandgap(Vdd,gnd,Vbg,Temp); inoutVdd,gnd,Vbg,Temp; electricalVdd,gnd,Temp; parameterrealVbg=1.2; analogbegin397第4期 朱樟明,张春朋等:基于Verilog-A的模拟电路行为模型及仿真 图1 CMOS带隙基准电压源 TempC=abs(Temp-27); Vbg+(Vbg+0.0011*(Vdd-1.5)-0.00001*TempC); EndendmoduleVerilog-A,1.2V,10-ppm/K1.1mV/V。CadenceSpectre,2(a),2(b)。(a) 温度特性(b) 电源特性图2 带隙基准电压源的行为模型仿真2.3 3。图3 全差分运算放大器电路3,,。,:、(PM)、、(VOS)、(CL)(RL)。(AC),AC。:`include”discipline.h”`include”constants.h”moduledvamp(vin-p,vin-n,vout-p,vout-n); inputvin-p,vin-n; outputvout-p,vout-n; electricalvin-p,vin-n,vout-p,vout-n; parameterrealgain=12000000.0; parameterrealoffset=0.0; realoutv; analogbegin outv=gain*(V(vin-p,vin-n)-offset); V(vout-p,vout-n)+outv; endendmodule,Verilog-A,、“initialblock”,,MOS(Slewing)(Cliping)。(Tail),Verilog-A。4Verilog-A。398 电子器件 第26卷图4全差分运放Verilog-A行为模型仿真波形3 Verilog-A 、,,SpiceSOC,Verilog-A。DAC(SFDR),Verilog-A(TestBench),SFDR。DACSFDR,(FFT),SFDR。DAC,Verilog-ADACADC,ADC,DAC。5DAC。图5 基于Verilog-A的DAC参数测试模型8bitDAC:`include“std.va”`include“const.va”moduledac8(d0,d1,d2,d3,d4,d5,d6,d7,out);inoutd0,d1,d2,d3,d4,d5,d6,d7,out;electricald0,d1,d2,d3,d4,d5,d6,d7,out;parameterrealref=1.2;…… initialbeginweight=0.0;for(i=0;i8;i=i+1)begin weight[i]=1.2/(pow(2,8-i)); error[i]=-(0.5-$random(48*i))/102.4; scale=scale+weight[i];end end analogbegin…… endendmodule68bitADC,1MHz。图6 8bit理想ADC的仿真波形4 Verilog-A,VerilogSOC。Verilog-A,、、,CadenceSpectre。SOC,DAC,。Verilog-ACadenceSpectre。:[1] ,.IP[J]..2002,25[2]:127-132.[2] OVILanguageReferenceManual[S].Version1.9.[3] MillerIra,ThierryCassagnes.Verilog-AMSEasesMixedModeSignalSimulation[C].2001.Boston.Nanotech2001.399第4期 朱樟明,张春朋等:基于Verilog-A的模拟电路行为模型及仿真
本文标题:基于Verilog-A的模拟电路行为模型及仿真-朱樟明
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