DDR-and-DDR2-SDRAM-High-Performance-Controller-Use

101InnovationDriveSanJose,CA95134:March2009Copyright©2009AlteraCorporation.Allrightsreserved.Altera,TheProgrammableSolutionsCompany,thestylizedAlteralogo,specificdevicedesignations,andallotherwordsandlogosthatareidentifiedastrademarksand/orservicemarksare,unlessnotedotherwise,thetrademarksandservicemarksofAlteraCorporationintheU.S.andothercountries.Allotherproductorservicenamesarethepropertyoftheirrespectiveholders.AlteraproductsareprotectedundernumerousU.S.andforeignpatentsandpendingap-plications,maskworkrights,andcopyrights.AlterawarrantsperformanceofitssemiconductorproductstocurrentspecificationsinaccordancewithAltera'sstandardwarranty,butreservestherighttomakechangestoanyproductsandservicesatanytimewithoutnotice.Alteraassumesnoresponsibilityorliabilityarisingoutoftheapplicationoruseofanyinformation,product,orservicedescribedhereinexceptasexpresslyagreedtoinwritingbyAlteraCorporation.Alteracustomersareadvisedtoobtainthelatestversionofdevicespecificationsbeforerelyingonanypublishedinformationandbeforeplacingordersforproductsorservices.UG-01010-7.0©March2009AlteraCorporationDDRandDDR2SDRAMHigh-PerformanceControllerUserGuideContentsChapter1.AboutTheseMegaCoreFunctionsReleaseInformation.....................................................................1–1DeviceFamilySupport...................................................................1–1Features................................................................................1–2GeneralDescription.....................................................................1–2MegaCoreVerification...................................................................1–3PerformanceandResourceUtilization......................................................1–4InstallationandLicensing................................................................1–7OpenCorePlusEvaluation.............................................................1–7OpenCorePlusTime-OutBehavior......................................................1–8Chapter2.GettingStartedDesignFlow............................................................................2–1SelectFlow.............................................................................2–2SOPCBuilderFlow......................................................................2–2SpecifyParameters....................................................................2–2CompletetheSOPCBuilderSystem.....................................................2–3SimulatetheSystem...................................................................2–4MegaWizardPlug-InManagerFlow.......................................................2–4SpecifyParameters....................................................................2–5SimulatetheExampleDesign...........................................................2–8SimulatingUsingNativeLink........................................................2–8IPFunctionalSimulations............................................................2–9CompiletheDesign.....................................................................2–13ProgramDeviceandImplementtheDesign................................................2–14Chapter3.ParameterSettingsMemorySettings........................................................................3–1PHYSettings...........................................................................3–1ControllerSettings.......................................................................3–1Chapter4.FunctionalDescriptionBlockDescription.......................................................................4–2CommandFIFO....................................................................4–3WriteDataFIFO....................................................................4–3WriteDataTrackingLogic...........................................................4–3MainStateMachine.................................................................4–3BankManagementLogic............................................................4–3TimerLogic........................................................................4–3InitializationStateMachine..........................................................4–4AddressandCommandDecode......................................................4–4PHYInterfaceLogic.................................................................4–4ODTGenerationLogic..............................................................4–4LowPowerModeLogic.............................................................4–4ControlLogic.........................................................................4–5Latency..............................................................................4–5ErrorCorrectionCoding(ECC).........................................................4–7Interrupts.........................................................................4–9ivDDRandDDR2SDRAMHigh-PerformanceControllerUserGuide©March2009AlteraCorporationPar