东南大学计算结构CPU报告

ComputerOrganizationandArchitectureCOURSEDESIGNNAMESTUDENTNUMBERCOURSEComputerOrganizationandArchitectureCourseDesignPROJECTACentralProcessingUnit(CPU)BasingOnVerilogHDLSOFTWAREPLATFORMISE14.1DATEAPR.15.20141.Purpose(1)ThepurposeofthisprojectistodesignasimpleCPU(CentralProcessingUnit).ThisCPUhasbasicinstructionset,andwewillutilizeitsinstructionsettogenerateaverysimpleprogramtoverifyitsperformance.Forsimplicity,wewillonlyconsidertherelationshipamongtheCPU,registers,memoryandinstructionset.Thatistosayweonlyneedconsiderthefollowingitems:Read/WriteRegisters,Read/WriteMemoryandExecutetheinstructions.AtleastfourpartsconstituteasimpleCPU:thecontrolunit,theinternalregisters,theALUandinstructionset,whicharethemainaspectsofourprojectdesignandwillbestudied.(2)TheuseofISEsoftwarefordesignandsimulation.2.TasksSingle-addressinstructionformatisusedinoursimpleCPUdesign.Theinstructionwordcontainstwosections:theoperationcode(opcode),whichdefinesthefunctionofinstructions(addition,subtraction,logicoperations,etc.);theaddresspart,inmostinstructions,theaddresspartcontainsthememorylocationofthedatumtobeoperated,wecalleditdirectaddressing.Insomeinstructions,theaddresspartistheoperand,whichiscalledimmediateaddressing.Forsimplicity,thesizeofmemoryis256×16inthecomputer.Theinstructionwordhas16bits.Theopcodeparthas8bitsandaddressparthas8bits.TheinstructionwordformatcanbeexpressedinFigure1.Figure1.TheinstructionformatTheopcodeoftherelevantinstructionsarelistedinTable1.InstructionOPCODECommentsADDX00000001ACC+[X]-ACCSUBX00000010ACC-[X]-ACCANDX00000011ACCand[X]-ACCORX00000100ACCor[X]-ACCNOTX00000101NOT[X]-ACCSHIFTR00000110SHIFTACCtoRight1bit,LogicShiftSHIFTL00000111SHIFTACCtoLeft1bit,LogicShiftMPYX00001000ACC×[X]-ACCDIVX00001001ACC÷[X]-ACCJMPGEZX00001010IfACC≥0thenX-PCelsePC+1-PCJMPX00001011X-PCHALT00001100HaltaprogramSTOREX00001101ACC-[X]LOADX00001110[X]-ACCTable1.Listofinstructionsandrelevantopcodes3.TheoverallconnectionexpressedinthetopmoduleformFigure2.Theoverallconnectionexpressedinthetopmoduleform4.InternalRegistersandMemory4.1Memory(Dist_mem_gen_v7_1)TheXilinxLogiCORE™IPDistributedMemoryGeneratorcoreusesXilinxSynthesisTechnology(XST)tocreateavarietyofdistributedmemories.Itgeneratesread-onlymemories(ROMs),single,simpledual,anddual-portrandomaccessmemories(RAMs),andSRL16-basedmemories;Supportsdatadepthsrangingfrom16–65,536words;Supportsdatawidthsrangingfrom1–1024bits.ThismemoryisasingleportRAMgeneratedbyDist_mem_gen_v7_1.4.2MAR(MemoryAddressRegister)MARcontainsthememorylocationofthewordtobereadfromthememoryorwrittenintothememory.Here,READoperationisdenotedastheCPUreadsfrommemory,andWRITEoperationisdenotedastheCPUwritestomemory.Inourdesign,MARhas8bitstoaccessoneof256addressesofthememory.4.3MBR(MemoryBufferRegister)MBRcontainsthevaluetobestoredinmemoryorthelastvaluereadfrommemory.MBRisconnectedtotheaddresslinesofthesystembus.Inourdesign,MBRhas16bits.Themodulehasbeenhorizontallyinverted.4.4PC(ProgramCounter)PCkeepstrackoftheinstructionstobeusedintheprogram.Inourdesign,PChas8bits.4.5IR(InstructionRegister)IRcontainstheopcodepartofaninstruction.Inourdesign,IRhas8bits.4.6ACC(Accumulator)ACCholdsoneoperandforALU,andgenerallyACCholdsthecalculationresultofALU.Inourdesign,ACChas16bits.BRisusedasaninputofALU,itholdsotheroperandforALU.Inourdesign,BRhas16bits.Themodulehasbeenhorizontallyinverted.4.7ALU(ArithmeticLogicUnit)ALUisacalculationunitwhichaccomplishesbasicarithmeticandlogicoperations.Inourdesign,someoperationsmustbesupportedwhicharelistedasfollows:Table2.ALUOperations4.8CU(MicroprogrammedControlUnit)WehavelearnttheknowledgeofMicroprogrammedcontrolunit.Here,weonlyreviewsometermsandbasicstructures.IntheMicroprogrammedcontrol,themicroprogramconsistsofsomemicroinstructionsandthemicroprogramisstoredincontrolmemorythatgeneratesallthecontrolsignalsrequiredtoexecutetheinstructionsetcorrectly.Themicroinstructioncontainssomemicro-operationswhichareexecutedatthesametime.Figure3showsthekeyelementsofsuchanimplementation.Thesetofmicroinstructionsisstoredinthecontrolmemory.Thecontroladdressregistercontainstheaddressofthenextmicroinstructionstoberead.Whenamicroinstructionisreadfromthecontrolmemory,itistransferredtoacontrolbufferregister.Theregisterconnectstothecontrollinesemanatingfromthecontrolunit.Thus,readingamicroinstructionfromthecontrolmemoryisthesameasexecutingthatmicroinstruction.Thethirdelementshowninthefigureisasequencingunitthatloadsthecontroladdressregisterandissuesareadcommand.Figure3.ControlUnitMicro-architectureInmydesign,IsimplifythestructureofMU.Figure4showstheControlUnitMicro-architectureinmydesign.CMisaDistributedROMgeneratedbyDist_mem_gen_v7_1.Itsfunctionisthesamewiththecontrolmemoryplusthecontrolbufferregisterinfigure3.Similarly,theSequencingLogic’sfunctionisthesamewithsequencinglogicpluscontroladdressregisterinfigure3.Figure4.ControlUnitMicro-architectureinmydesignControlSignalsCM地址控制C0CAR=CAR+1C1CAR=***C2CAR=0系统总线C3RWmemoryC5Wmemory数据通路C4memory=MBRC6MBR=memoryC7IR=MBR[15..8]C8MAR=MBR[7..0]C9BR=MBRC10PC=MBRC11M