TSMC-0.25和0.35um-设计规则

TSMC工艺设计规则]2-Page1of212设计规则2.1设计规则几何关系定义Width：Sapcing:Extension：一几何图形内边界到另一图形外边界长度Overlap：一几何图形内边界到另一图形内边界长度TSMC工艺设计规则]2-Page2of212.2设计规则[TSMC_0.35_4M2P_SUBM]lambda＝0.2um[TSMC_0.25_5M1P_DEEP]lambda＝0.12um2.2.1Well[1.1-1.4]RuleDescriptionSUBMDEEP1.1Minimumwidth12121.2Minimumspacingbetweenwellsatdifferentpotential18181.3Minimumspacingbetweenwellsatsamepotential661.4Minimumspacingbetweenwellsofdifferenttype00TSMC工艺设计规则]2-Page3of212.2.2Active[2.1-2.5]RuleDescriptionSUBMDEEP2.1Minimumwidth332.2Minimumspacing332.3Source/drainactivetowelledge662.4Substrate/wellcontactactivetowelledge332.5Minimumspacingbetweenactiveofdifferentimplant44TSMC工艺设计规则]2-Page4of212.2.3ThickActive[24.1-24.5]THICK_ACTIVEisalayerusedforthoseprocessesofferingtwodifferentthicknessesofgateoxide(typicallyforthelayoutoftransistorsthatoperateattwodifferentvoltagelevels).TheACTIVElayerisusedtodelineatealltheactiveareas,regardlessofgateoxidethickness.THICK_ACTIVEisusedtotomarkthoseACTIVEareasthatwillhavethethickergateoxide;ACTIVEareasoutsideTHICK_ACTIVEwillhavethethinnergateoxide.RuleDescriptionSUBMDEEP24.1Minimumwidth4424.2Minimumspacing4424.3MinimumACTIVEoverlap4424.4MinimumspacetoexternalACTIVE4424.5MinimumpolywidthinaTHICK_ACTIVEgate33TSMC工艺设计规则]2-Page5of212.2.4Poly[3.1-3.5]RuleDescriptionSUBMDEEP3.1Minimumwidth223.2Minimumspacingoverfield333.2.aMinimumspacingoveractive343.3Minimumgateextensionofactive22.53.4Minimumactiveextensionofpoly343.5Minimumfieldpolytoactive11TSMC工艺设计规则]2-Page6of212.2.5SilicideBlock[20.1-20.9]RuleDescriptionDEEP20.1MinimumSBwidth420.2MinimumSBspacing420.3Minimumspacing,SBtocontact(nocontactsallowedinsideSB)220.4Minimumspacing,SBtoexternalactive220.5Minimumspacing,SBtoexternalpoly220.6ResistorispolyinsideSB;polyendsstickoutforcontactstheentireresistormustbeoutsidewellandoverfieldN/A20.7Minimumpolywidthinresistor520.8Minimumspacingofpolyresistors(inasingleSBregion)720.9MinimumSBoverlapofpoly2TSMC工艺设计规则]2-Page7of212.2.6Select[4.1-4.4]RuleDescriptionSUBMDEEP4.1Minimumselectspacingtochanneloftransistor334.2Minimumselectoverlapofactive224.3Minimumselectoverlapofcontact11.54.4Minimumselectwidthandspacing(Note:P-selectandN-selectmaybecoincident,butmustnotoverlap)24TSMC工艺设计规则]2-Page8of212.2.7ElectrodeforCapacitor[11.1-11.6]Thepoly2layerisasecondpolysiliconlayer(physicallyabovethestandard,orfirst,polylayer).Theoxidebetweenthetwopolysisthecapacitordielectric.Thecapacitorareaistheareaofcoincidentpolyandelectrode.RuleDescriptionSUBMDEEP11.1Minimumwidth7n/a11.2Minimumspacing311.3Minimumpolyoverlap511.4Minimumspacingtoactiveorwelledge(notillustrated)211.5Minimumspacingtopolycontact611.6Minimumspacingtounrelatedmetal2TSMC工艺设计规则]2-Page9of212.2.8ElectrodeContact[13.1-13.5]Thepoly2iscontactedthroughthestandardcontactlayer,similartothefirstpoly.Theoverlapnumbersarelarger,however.RuleDescriptionSUBMDEEP13.1Exactcontactsize2x2n/a13.2Minimumcontactspacing313.3Minimumelectrodeoverlap(oncapacitor)313.4Minimumelectrodeoverlap(notoncapacitor)213.5Minimumspacingtopolyoractive3TSMC工艺设计规则]2-Page10of212.2.9ContacttoPoly[5.1-5.4]RuleDescriptionSUBMDEEP5.1Exactcontactsize2x22x25.2Minimumpolyoverlap1.51.55.3Minimumcontactspacing345.4Minimumspacingtogateoftransistor22TSMC工艺设计规则]2-Page11of212.2.10ContacttoActive[6.1-6.4]RuleDescriptionSUBMDEEP6.1Exactcontactsize2x22x26.2Minimumactiveoverlap1.51.56.3Minimumcontactspacing346.4Minimumspacingtogateoftransistor22TSMC工艺设计规则]2-Page12of212.2.11Metal1[7.1-7.4]RuleDescriptionSUBMDEEP7.1Minimumwidth337.2Minimumspacing337.3Minimumoverlapofanycontact117.4Minimumspacingwhenmetallineiswiderthan10lambda66TSMC工艺设计规则]2-Page13of212.2.12Via[8.1-8.5]RuleDescriptionSUBMDEEP8.1Exactsize2x23x38.2Minimumvia1spacing338.3Minimumoverlapbymetal1118.4Minimumspacingtocontact2n/a8.5Minimumspacingtopolyoractiveedge2n/aTSMC工艺设计规则]2-Page14of212.2.13Metal2[9.1-9.4]RuleDescriptionSUBMDEEP9.1Minimumwidth339.2Minimumspacing349.3Minimumoverlapofvia1119.4Minimumspacingwhenmetallinewiderthan10lambda68TSMC工艺设计规则]2-Page15of212.2.14Via2[14.1-14.4]RuleDescriptionSUBMDEEP14.1Exactsize2x23x314.2Minimumspacing3314.3Minimumoverlapbymetal21n/a14.4Minimumspacingtovia12n/aTSMC工艺设计规则]2-Page16of212.2.14Metal3[15.1-15.4]RuleDescriptionSUBMDEEP15.1Minimumwidth3315.2Minimumspacingtometal33415.3Minimumoverlapofvia21115.4Minimumspacingwhenmetallineiswiderthan10lambda68TSMC工艺设计规则]2-Page17of212.2.15Via3[21.1-21.3]RuleDescriptionSUBMDEEP21.1Exactsize2x23x321.2Minimumspacing3321.3MinimumoverlapbyMetal311TSMC工艺设计规则]2-Page18of212.2.16Metal4[21.1-21.4]RuleDescriptionSUBMDEEP22.1METAL4width6322.2METAL4space6422.3METAL4overlapofVIA32122.4Minimumspacingwhenmetallineiswiderthan10lambda128TSMC工艺设计规则]2-Page19of212.2.17CAP_TOP_METAL[28.1-28.6]TheCAP_TOP_METALlayerisusedexclusivelyfortheconstructionofmetal-to-metalcapacitors.Thebottomplateofthecapacitorisoneoftheregularmetallayers,asspecifiedbelow.CAP_TOP_METAListheupperplateofthecapacitor;itissandwichedphysicallybetweenthebottomplatemetalandthenextmetallayerabove,withathindielectricbetweenthebottomandtopplates.TheCAP_TOP_METALcan