MIPS指令单周期CPU设计

指令的执行步骤典型指令的数据通路组装数据通路典型指令的控制信号控制器设计4.3MIPS指令单周期CPU设计计算机一条指令的执行时间被称为指令周期，一个CPU时钟时间被称为CPU周期(在某些计算机中，还可再把一个CPU周期区分为几个更小的步骤，称其为节拍)。执行每条指令平均使用的CPU周期个数被称为CPI。全部指令都选用一个CPU周期完成的系统被称为单周期CPU，指令串行执行，前一条指令结束后才启动下条指令。每条指令都用5个步骤的时间完成，控制各部件运行的信号在整个指令周期不变化。单周期CPU用于早期计算机，系统性能和资源利用率很低，相对当前技术变得不再实用。IFIDEXEMEMWBCPI=1一、指令执行步骤-单周期CPUCPU周期IFIDEXEMEMWB指令周期执行步骤(1/5)Phase1:InstructionFetch(IF)–Fetch32-bitinstructionfrommemory–IncrementPC(PC=PC+4)1.InstructionFetch2.Decode/RegisterRead3.Execute4.Memory5.RegisterWritePCinstructionmemory+4RegisterFilertrsrdALUDatamemoryimmMUX1.InstructionFetchPhase2:InstructionDecode(ID)–Readtheopcodeandappropriatefieldsfromtheinstruction–GatherallnecessaryregistersvaluesfromRegisterFile1.InstructionFetch2.Decode/RegisterRead3.Execute4.Memory5.RegisterWritePCinstructionmemory+4RegisterFilertrsrdALUDatamemoryimmMUX执行步骤(2/5)Phase3:Execute(EX)–ALUperformsoperations:arithmetic(+,-,*,/),shifting,logical(&,|),comparisons(slt,==)–Alsocalculatesaddressesforloadsandstores1.InstructionFetch2.Decode/RegisterRead3.Execute4.Memory5.RegisterWritePCinstructionmemory+4RegisterFilertrsrdALUDatamemoryimmMUX执行步骤(3/5)Phase4:MemoryAccess(MEM)–Onlyloadandstoreinstructionsdoanythingduringthisphase;theothersremainidleorskipthisphase–Shouldbefastduetocaches1.InstructionFetch2.Decode/RegisterRead3.Execute4.Memory5.RegisterWritePCinstructionmemory+4RegisterFilertrsrdALUDatamemoryimmMUX执行步骤(4/5)Phase5:RegisterWrite(WBfor“writeback”)–WritetheinstructionresultbackintotheRegisterFile–Thosethatdon’t(e.g.sw,j,beq)remainidleorskipthisphase1.InstructionFetch2.Decode/RegisterRead3.Execute4.Memory5.RegisterWritePCinstructionmemory+4RegisterFilertrsrdALUDatamemoryimmMUX执行步骤(5/5)单周期CPU设计思路指令的执行–显然要设计一个时序逻辑电路–一条指令用一个CPU周期完成执行步骤的实现–取指：从指令存储器中读指令（地址：PC）–读出一或两个源寄存器的值（寄存器组）–进行指令规定的运算（ALU）–读/写数据存储器–将结果写入目的寄存器需要保存的值–PC、寄存器组、存储器ADDUandSUBU–addurd,rs,rt–suburd,rs,rtORImmediate:–orirt,rs,imm16LOADandSTOREWord–lwrt,rs,imm16–swrt,rs,imm16BRANCH:–beqrs,rt,imm16oprsrtrdshamtfunct0611162126316bits6bits5bits5bits5bits5bitsoprsrtimmediate0162126316bits16bits5bits5bitsoprsrtimmediate0162126316bits16bits5bits5bitsoprsrtimmediate0162126316bits16bits5bits5bits二、典型指令的数据通路算术运算指令ADDU和SUBU–addurdrsrt–suburdrsrt1.MIPS指令——addu\subu指令功能–R[rd]=R[rs]+R[rt]–R[rd]=R[rs]–R[rt]PCinstructionmemoryRegisterFilertrsrdALU+42.MIPS指令——ori逻辑运算ori–orirtrsimm指令功能–R[rt]=R[rs]ORZeroExt(imm)PCinstructionmemoryRegisterFilertrsrdALU+4imm3.MIPS指令—Load/Store读指令load–lwrtrsimm–Addr=R[rs]+SignExt(imm)–R[rt]=MEM[Addr]写指令storeswrtrsimmAddr=R[rs]+SignExt(imm)MEM[Addr]=R[rt]PCinstructionmemoryRegisterFilertrsrdALU+4immDatamemory4.MIPS指令——BEQ比较指令BEQ–beqrsrtimm–ifR[rs]=R[rt]–thenPC(PC+4)+SignExt(imm)–ElsePCPC+4PCinstructionmemoryRegisterFilertrsrdALU+4immDatamemoryMUX5.MIPS指令——Jump跳转指令Jtarget–PC[31:0]PC[31:28]||target[25:0]||[00]PCinstructionmemory+4RegisterFilertrsrdALUDatamemoryimmMUX组合逻辑部件－Gatesandwires32AB32Y32SelectMUXMultiplexerALU3232AB32ResultOPALU3232AB32SumCarryOutCarryInAdderAdder三、组装数据通路CLKDataInWriteEnable3232DataOutAddress时序逻辑部件－Memory、RegisterandRegisterFileCLKDataInWriteEnableNNDataOutClkbusWWriteEnable3232busA32busB555RWRARB32x32-bitRegistersNextAddressLogic32InstructionAddressInstructionMemoryPCCLKWiresandSplitters32Instr55556166opcodersrtrdshamtfunctimm公操作部件－IF部件、ID部件ADDUR[rd]R[rs]+R[rt];Hardwareneeded:–InstructionMemandPC(alreadyshown)–RegisterFile(RegFile)forreadandwrite–ALUforadd/subtractCLKbusW3232busA32busB555RWRARB32x32-bitRegisters32ResultALU32A32BADDUR[rd]R[rs]+R[rt];Connections:–RegFileandALUInputs–ConnectRegFileandALU–RegWr(1)andALUctr(ADD/SUB)setbycontrolinID32ResultCLKbusW3232busA32busB555RWRARB32x32-bitRegistersALUctrRegWrrsrtrdALU32A32BORIR[rt]R[rs]|zero_ext(Imm16);Isthehardwarebelowsufficient?–Zeroextendimm16?–Passimm16toinputofALU?–Writeresulttort?32ResultCLKbusW3232busA32busB555RWRARB32x32-bitRegistersALUctrRegWrrsrtrdALUORIR[rt]R[rs]|zero_ext(Imm16);Addnewhardware:–Stillsupportadd/sub–Newcontrolsignals:RegDst,ALUSrc32ALUctrCLKRegWr3232busA32busB55RWRARBRegFilersrtrtrdZeroExt3216imm16ALUSrc0101ALU5RegDst2:1MUXHowtoimplementthis?LOADR[rt]MEM[R[rs]+sign_ext(Imm16)];Hardwaresufficient?–Signextendimm16?–Where’sMEM?32ALUctrCLKRegWr3232busA32busB55RWRARBRegFilersrtrtrdZeroExt3216imm16ALUSrc0101ALU5RegDstLOADR[rt]MEM[R[rs]+sign_ext(Imm16)];Newcontrolsignals:ExtOp,MemWr,MemtoReg32ALUctrCLKbusWRegWr3232busA32busB55RWRARBRegFilersrtrtrdRegDstExtender3216imm16ALUSrcExtOpMemtoRegCLKDataIn32MemWr0101ALU01WrEnAddrDataMemory5???alsohandlesignextensionWhatgoeshereduringastore?STOREMEM[R[rs]+sign_ext(Imm16)]R[rt];ConnectbusBtoDataIn(noextracontrolneeded!)32ALUctrCLKbusWRegWr3232busA32busB55RWRARBRegFilersrtrtrdRegDstExtender3216imm16ALUSrcExtOpMemtoRegCLKDataIn32MemWr0101ALU01WrEnAddrDataMemory5BEQif(R[rs]==R[rt])thenPCPC+4+(sign_ext(Imm16)||00)NeedcomparisonoutputfromALU32ALUctrCLKbusWRegWr3232busA32busB55RWRARBRegFilersrtrtrdRegDstExtender3216imm16ALUSrcExtOpMemtoRegCLKDataIn32MemWr0101ALU01WrEnAddrDataMemory5zero=NextAddre