JZ4750_05.2_emc_spec

ExternalMemoryControllerXBurstJZ4750programmanual,Revision1.0Copyright®2005-2010IngenicSemiconductorCo.,Ltd.Allrightsreserved.11ExternalMemoryController1.1OverviewTheExternalMemoryController(EMC)dividestheoff-chipmemoryspaceandoutputscontrolsignalscomplyingwithspecificationsofvarioustypesofmemoryandbusinterfaces.Itenablestheconnectionofstaticmemory,NANDflashmemory,synchronousDRAM,etc.,tothisprocessor.zStaticmemoryinterface–DirectinterfacetoROM,BurstROM,SRAMandNORFlash.–Support4externalchipselectionCS4~1#.Eachbankcanbeconfiguredseparately.–Thesizeandbaseaddressofstaticmemorybanksareprogrammable.–Outputofcontrolsignalsallowingdirectconnectionofmemorytoeachbank.Writestrobesetuptimeandholdtimeperiodscanbeinsertedinanaccesscycletoenableconnectiontolow-speedmemory–Waitstateinsertioncanbecontrolledbyprogram.–WaitinsertionbyWAITpin.–Automaticwaitcycleinsertiontopreventdatabuscollisionsincaseofconsecutivememoryaccessestodifferentbanks,orareadaccessfollowedbyawriteaccesstothesamebankzNANDflashinterface–SupportonCS4~CS1,sharingwithstaticmemorybank4~bank1.–SupportmosttypesofNANDflashes,including8-bitand16-bitbuswidth,512Band2KBpagesize.For512Bpagesize,3and4addresscyclesaresupported.For2KBpagesize,4and5addresscyclesaresupported.–Supportread/erase/programNANDflashmemory.–SupportbootfromNANDflash.zSDRAMInterface–Support2chipselectionDCS0#andDCS1#.–Supportboth32-bitand16-bitbuswidth.–Supportbothtwo-bankandfour-banktypeSDRAM.–Supportburstoperation.–Supportbothauto-refreshandself-refreshfunctions.–Thesizeandbaseaddressofeachbankisconfigurable.–Multiplexesrow/columnaddressesaccordingtoSDRAMcapacity–ControlstimingofSDRAMdirect-connectioncontrolsignalsaccordingtoregistersetting–Supportspower-downmodetominimizethepowerconsumptionofSDRAM–SupportpagemodeExternalMemoryControllerXBurstJZ4750programmanual,Revision1.0Copyright®2005-2010IngenicSemiconductorCo.,Ltd.Allrightsreserved.21.2PinDescriptionFollowingtablelisttheEMCpins.Table1-1EMCPinDescriptionPinNameI/OSignalDescriptionDataBusI/OD31–D0DataI/OAddressbusOA25–A0AddressoutputStaticchipselect4~1OCS4~1#ChipselectsignalthatindicatesthestaticbankbeingaccessedSDRAMchipselectODCS0#ChipselectsignalthatindicatestheSDRAMbankbeingaccessedSDRAMchipselectODCS1#ChipselectsignalthatindicatestheSDRAMbankbeingaccessedReadenableORD#/ForStaticmemoryreadenablesignalWriteenableOWE#/StaticmemorywriteenablesignalColumnaddressstrobeOCAS#SDRAMcolumnaddressstrobesignalRowaddressstrobeORAS#SDRAMrowaddressstrobesignalRead/writeORD/WR#DatabusdirectiondesignationsignalAlsousedasSDRAMwriteenablesignalByteenable0OWE0#/BE0#/DQM0/Fornon-byte-controlstaticmemory,D7-0writeenablesignal,Forbyte-controlstaticmemory,D7-0selectionsignalForSDRAM,D7–D0selectionsignalByteenable1OWE1#/BE1#/DQM1/Fornon-byte-controlstaticmemory,D15-8writeenablesignalForbyte-controlstaticmemory,D15-8selectionsignalForSDRAM,D15–D8selectionsignalByteenable2OWE2#/BE2#/DQM2/Fornon-byte-controlstaticmemory,D23-16writeenablesignalForbyte-controlstaticmemory,D23-16selectionsignalForSDRAM,D23–D16selectionsignalByteenable3OWE3#/BE3#/DQM3Forstaticmemory,D31-24writeenablesignalForbyte-controlstaticmemory,D31-24selectionsignalForSDRAM,D31–D24selectionsignal.SDRAMClockenableOCKEEnabletheSDRAMclockSDRAMClockOCKOSDRAMclockWaitIWait#/Externalwaitstaterequestsignalformemory-likedevicesNANDflashreadenableOFRE#NANDflashreadenablesignalNANDflashwriteenableOFWE#NANDflashwriteenablesignalNANDflashready/busyIFRB#IndicatesNANDflashisreadyorbusy(WhenNandflashboot,GPC30isusedasFRB#ofCS1#)ExternalMemoryControllerXBurstJZ4750programmanual,Revision1.0Copyright®2005-2010IngenicSemiconductorCo.,Ltd.Allrightsreserved.31.3PhysicalAddressSpaceMapBothvirtualspacesandphysicalspacesare32-bitwideinthisarchitecture.VirtualaddressesaretranslatedbyMMUintophysicaladdresswhichisfurtherdividedintoseveralpartitionsforstaticmemory,SDRAM,andinternalI/O.Figure1-1PhysicalAddressSpaceMap0xE00000000xFFFFFFFF0x000000000x20000000InternalI/OSpace(64MB)SDRAMChangeableBaseAddressChangeableSize(2944MBMax)ReservedSpace(512MB)DefaultSDRAMBank(128MB)DefaultStaticMemoryBank0(64MB)SDRAMSpace(128MB)0x100000000x08000000ReservedReservedOn-chipBootROM(8KB)0x1FFFFFFF0x1FC000000x1C0000000x1FC020000x0C0000000x140000000x180000000x1C000000DefaultStaticMemoryBank4(8MB)DefaultStaticMemoryBank3(8MB)DefaultStaticMemoryBank2(8MB)DefaultStaticMemoryBank1(8MB)ExternalMemoryControllerXBurstJZ4750programmanual,Revision1.0Copyright®2005-2010IngenicSemiconductorCo.,Ltd.Allrightsreserved.4Table1-2PhysicalAddressSpaceMapStartAddressEndAddressConnectableMemoryCapacityH’00000000H’07FFFFFSDRAMspace128MBH’08000000H’0FFFFFFFStaticmemoryspace128MBH’10000000H’13FFFFFFInternalI/Ospace64MBH’14000000H’1BFFFFFFStaticmemoryspace128MBH’1C000000H’1FBFFFFFUn-used60MBH’1FC00000H’1FC01FFFOn-chipbootROM8KBH’1FC01000H’1FFFFFFFUn-used4095KBH’20000000H’BFFFFFFFSDRAMspace2944MBH’D0000000H’FFFFFFFFReservedspace512MBThebaseaddressandsizeofeachmemorybanksareconfigurable.Softwarecanre-configurethesememorybanksaccordingtotheactualconnectedmemories.Fol