STM32高速USB-原理图

1122334455667788DDCCBBAATitleNumberRevisionSizeA3Date:2016/1/14SheetofFile:F:\OtherWork\..\USB2XXX.SchDocDrawnBy:PA0-WKUP(PA0)/USART2_CTS/UART4_TX/ETH_MII_CRS/TIM2_CH1_ETR/TIM5_CH1/TIM8_ETR/EVENTOUT/ADC123_IN0/WKUP23PA1/USART2_RTS/UART4_RX/ETH_RMII_REF_CLK/ETH_MII_RX_CLK/TIM5_CH2/TIM2_CH2/EVENTOUT/ADC123_IN124PA2/USART2_TX/TIM5_CH3/TIM9_CH1/TIM2_CH3/ETH_MDIO/EVENTOUT/ADC123_IN225PA3/USART2_RX/TIM5_CH4/TIM9_CH2/TIM2_CH4/OTG_HS_ULPI_D0/ETH_MII_COL/EVENTOUT/ADC123_IN326PA4/SPI1_NSS/SPI3_NSS/USART2_CK/DCMI_HSYNC/OTG_HS_SOF/I2S3_WS/EVENTOUT/ADC12_IN4/DAC1_OUT29PA5/SPI1_SCK/OTG_HS_ULPI_CK/TIM2_CH1_ETR/TIM8_CHIN/EVENTOUT/ADC12_IN5/DAC2_OUT30PA6/SPI1_MISO/TIM8_BKIN/TIM13_CH1/DCMI_PIXCLK/TIM3_CH1/TIM1_BKIN/EVENTOUT/ADC12_IN631PA7/SPI1_MOSI/TIM8_CH1N/TIM14_CH1/TIM3_CH2/ETH_MII_RX_DV/TIM1_CH1N/RMII_CRS_DV/EVENTOUT/ADC12_IN732PA8/MCO1/USART1_CK/TIM1_CH1/I2C3_SCL/OTG_FS_SOF/EVENTOUT67PA9/USART1_TX/TIM1_CH2/I2C3_SMBA/DCMI_D0/EVENTOUT/OTG_FS_VBUS68PA10/USART1_RX/TIM1_CH3/OTG_FS_ID/DCMI_D1/EVENTOUT69PA11/USART1_CTS/CAN1_RX/TIM1_CH4/OTG_FS_DM/EVENTOUT70PA12/USART1_RTS/CAN1_TX/TIM1_ETR/OTG_FS_DP/EVENTOUT71PA13(JTMS-SWDIO)/JTMS-SWDIO/EVENTOUT72PA14(JTCK-SWCLK)/JTCK-SWCLK/EVENTOUT76PA15(JTDI)/JTDI/SPI3_NSS/I2S3_WS/TIM2_CH1_ETR/SPI1_NSS/EVENTOUT77PB0/TIM3_CH3/TIM8_CH2N/OTG_HS_ULPI_D1/ETH_MII_RXD2/TIM1_CH2N/EVENTOUT/ADC12_IN835PB1/TIM3_CH4/TIM8_CH3N/OTG_HS_ULPI_D2/ETH_MII_RXD3/OTG_HS_INTN/TIM1_CH3N/EVENTOUT/ADC12_IN936PB2-BOOT1(PB2)/EVENTOUT37PB3(JTDO/TRACESWO)/JTDO/TRACESWO/SPI3_SCK/I2S3_CK/TIM2_CH2/SPI1_SCK/EVENTOUT89PB4(NJTRST)/NJTRST/SPI3_MISO/TIM3_CH1/SPI1_MISO/I2S3ext_SD/EVENTOUT90PB5/I2C1_SMBA/CAN2_RX/OTG_HS_ULPI_D7/ETH_PPS_OUT/TIM3_CH2/SPI1_MOSI/SPI3_MOSI/DCMI_D10/I2S3_SD/EVENTOUT91PB6/I2C1_SCL/TIM4_CH1/CAN2_TX/DCMI_D5/USART1_TX/EVENTOUT92PB7/I2C1_SDA/FSMC_NL/DCMI_VSYNC/USART1_RX/TIM4_CH2/EVENTOUT93PB8/TIM4_CH3/SDIO_D4/TIM10_CH1/DCMI_D6/ETH_MII_TXD3/I2C1_SCL/CAN1_RX/EVENTOUT95PB9/SPI2_NSS/I2S2_WS/TIM4_CH4/TIM11_CH1/SDIO_D5/DCMI_D7/I2C1_SDA/CAN1_TX/EVENTOUT96PB10/SPI2_SCK/I2S2_CK/I2C2_SCL/USART3_TX/OTG_HS_ULPI_D3/ETH_MII_RX_ER/TIM2_CH3/EVENTOUT47PB11/I2C2_SDA/USART3_RX/OTG_HS_ULPI_D4/ETH_RMII_TX_EN/ETH_MII_TX_EN/TIM2_CH4/EVENTOUT48PB12/SPI2_NSS/I2S2_WS/I2C2_SMBA/USART3_CK/TIM1_BKIN/CAN2_RX/OTG_HS_ULPI_D5/ETH_RMII_TXD0/ETH_MII_TXD0/OTG_HS_ID/EVENTOUT51PB13/SPI2_SCK/I2S2_CK/USART3_CTS/TIM1_CH1N/CAN2_TX/OTG_HS_ULPI_D6/ETH_RMII_TXD1/ETH_MII_TXD1/EVENTOUT/OTG_HS_VBUS52PB14/SPI2_MISO/TIM1_CH2N/TIM12_CH1/OTG_HS_DM/USART3_RTS/TIM8_CH2N/I2S2ext_SD/EVENTOUT53PB15/SPI2_MOSI/I2S2_SD/TIM1_CH3N/TIM8_CH3N/TIM12_CH2/OTG_HS_DP/EVENTOUT54U1ASTM32F407VGT6PC0/OTG_HS_ULPI_STP/EVENTOUT/ADC123_IN1015PC1/ETH_MDC/EVENTOUT/ADC123_IN1116PC2/SPI2_MISO/OTG_HS_ULPI_DIR/TH_MII_TXD2/I2S2ext_SD/EVENTOUT/ADC123_IN1217PC3/SPI2_MOSI/I2S2_SD/OTG_HS_ULPI_NXT/ETH_MII_TX_CLK/EVENTOUT/ADC123_IN1318PC4/ETH_RMII_RX_D0/ETH_MII_RX_D0/EVENTOUT/ADC12_IN1433PC5/ETH_RMII_RX_D1/ETH_MII_RX_D1/EVENTOUT/ADC12_IN1534PC6/I2S2_MCK/TIM8_CH1/SDIO_D6/USART6_TX/DCMI_D0/TIM3_CH1/EVENTOUT63PC7/I2S3_MCK/TIM8_CH2/SDIO_D7/USART6_RX/DCMI_D1/TIM3_CH2/EVENTOUT64PC8/TIM8_CH3/SDIO_D0/TIM3_CH3/USART6_CK/DCMI_D2/EVENTOUT65PC9/I2S_CKIN/MCO2/TIM8_CH4/SDIO_D1//I2C3_SDA/DCMI_D3/TIM3_CH4/EVENTOUT66PC10/SPI3_SCK/I2S3_CK/UART4_TX/SDIO_D2/DCMI_D8/USART3_TX/EVENTOUT78PC11/UART4_RX/SPI3_MISO/SDIO_D3/DCMI_D4/USART3_RX/I2S3ext_SD/EVENTOUT79PC12/UART5_TX/SDIO_CK/DCMI_D9/SPI3_MOSI/I2S3_SD/USART3_CK/EVENTOUT80PC13/EVENTOUT/RTC_AF17PC14-OSC32_IN(PC14)/EVENTOUT/OSC32_IN8PC15-OSC32_OUT(PC15)/EVENTOUT/OSC32_OUT9PD0/FSMC_D2/CAN1_RX/EVENTOUT81PD1/FSMC_D3/CAN1_TX/EVENTOUT82PD2/TIM3_ETR/UART5_RX/SDIO_CMD/DCMI_D11/EVENTOUT83PD3/FSMC_CLK/USART2_CTS/EVENTOUT84PD4/FSMC_NOE/USART2_RTS/EVENTOUT85PD5/FSMC_NWE/USART2_TX/EVENTOUT86PD6/FSMC_NWAIT/USART2_RX/EVENTOUT87PD7/USART2_CK/FSMC_NE1/FSMC_NCE2/EVENTOUT88PD8/FSMC_D13/USART3_TX/EVENTOUT55PD9/FSMC_D14/USART3_RX/EVENTOUT56PD10/FSMC_D15/USART3_CK/EVENTOUT57PD11/FSMC_CLE/FSMC_A16/USART3_CTS/EVENTOUT58PD12/FSMC_ALE/FSMC_A17/TIM4_CH1/USART3_RTS/EVENTOUT59PD13/FSMC_A18/TIM4_CH2/EVENTOUT60PD14/FSMC_D0/TIM4_CH3/EVENTOUT/EVENTOUT61PD15/FSMC_D1/TIM4_CH4/EVENTOUT62U1BSTM32F407VGT6PE0/TIM4_ETR/FSMC_NBL0/DCMI_D2/EVENTOUT97PE1/FSMC_NBL1/DCMI_D3/EVENTOUT98PE2/TRACECLK/FSMC_A23/ETH_MII_TXD3/EVENTOUT1PE3/TRACED0/FSMC_A19/EVENTOUT2PE4/TRACED1/FSMC_A20/DCMI_D4/EVENTOUT3PE5/TRACED2/FSMC_A21/TIM9_CH1/DCMI_D6/EVENTOUT4PE6/TRACED3/FSMC_A22/TIM9_CH2/DCMI_D7/EVENTOUT5PE7/FSMC_D4/TIM1_ETR/EVENTOUT38PE8/FSMC_D5/TIM1_CH1N/EVENTOUT39PE9/FSMC_D6/TIM1_CH1/EVENTOUT40PE10/FSMC_D7/TIM1_CH2N/EVENTOUT41PE11/FSMC_D8/TIM1_CH2/EVENTOUT42PE12/FSMC_D9/TIM1_CH3N/EVENTOUT43PE13/FSMC_D10/TIM1_CH3/EVENTOUT44PE14/FSMC_D11/TIM1_CH4/EVENTOUT45PE15/FSMC_D12/TIM1_BKIN/EVENTOUT46U1CSTM32F407VGT6PH0-OSC_IN(PH0)/EVENTOUT/OSC_IN12PH1-OSC_OUT(PH1)/EVENTOUT/OSC_OUT13BOOT0/VPP94NRST14VCAP_149VCAP_273U1DSTM32F407VGT6VREF+21VBAT6VDD11VDD19VDD28VDD50VDD75VDD100VDDA22VSS10VSS27VSS74VSS99VSSA20U1ESTM32F407VGT6GND3.3VGNDGNDGNDXT18MGNDGNDR210KGNDR110K3.3VGNDFSMC_D0FSMC_D1FSMC_D2FSMC_D3FSMC_D4FSMC_D5FSMC_D6FSMC_D7FSMC_NOEGNDFLAG0GND1GND