Sub-50nm-FinFET--PMOS

Sub50-nmFinFET:PMOSXuejueHuang,Wen-ChinLee,CharlesKuo,DighHisamoto,LelandChang,JakubKedzierski,ErikAnderson**,HidekiTakeuchi,Yang-KyuChoi,KazuyaAsano,VivekSubramanian,Tsu-JaeKing,JeffreyBokorandChenmingHuDepartmentofElectricalEngineeringandComputerSciences,UniversityofCaliforniaatBerkeley,CA94720USATel:[phone];FAX:[phone];e-mail:[e-mail]*CentralResearchLaboratory,HitachiLtd.,Tokyo,Japan**LawrenceBerkeleyNationalLaboratory,UniversityofCalifornia,Berkeley,CA94720USANKKCorp.,JapanAbstractHighperformancePMOSFETswithgatelengthasshortas18-nmarereported.Aself-aligneddouble-gateMOSFETstructure(FinFET)isusedtosuppresstheshortchanneleffect.45nmgate-lengthPMOSFinFEThasanIdsatof410pNpm(or820pNpmdependingonthedefinitionofthewidthofadouble-gatedevice)atVd=Vg=1.2VandTox=2.5nm.Thequasi-planarnatureofthisvariantofthedouble-gateMOSFETsmakesdevicefabricationrelativelyeasyusingtheconventionalplanarMOSFETprocesstechnologies.Simulationshowspossiblescalingto10-nmgatelength.PolY-SiGeFigure1SchematicdrawingofFinFETFig.1showsanexplodedviewoftheFinFETdevice.Thefollowingprocesssequencewasusedtofabricatethedevice.100nmSO1filmoverburiedoxidewasthinnedto50nmbythermaloxidation.Ionimplantationestablishedabodydopingconcentrationofloi6~m-~.ThenLTOwasdepositedovertheSifilmasahardmaskmaterial.Using100keVe-beamlithographyandresistashingin02plasma,narrowSifinswerepatternedandetched.100nmin-situboron-dopedSiGeand300nmLTOhardmaskweredepositedoverthefin.SiGeisusedbecausetheresistivityofheavilydopedp-typepoly-Sil.,Ge,ismuchlowerthanthatofcomparablydopedpoly-Si[4].TheSiGeprovidesgoodelectricalcontactatthesidesurfacesoftheSifin.TheLTOandSiGefilmswereetchedtodelineateandseparatetheraisedsourceanddrainregions.Fig.2showstheS/Dwithagapin-between.VisibleinthegapistheSifinwiththeoxidehardmask.100nmnitridewasthendepositedandetchedtoformspacersontheside-wallsoftheS/D.Bysufficientoveretching,nitridewasremovedfromtheside-wallsofthefin.Fig.3showsa~20nmgapbetweentheS/Dspacers.(Thefinisdifficulttoseeatthecenterofthephoto.)Thewidthofthisspacergapatthesides(notthetopofthefinhardmask)determinesthegatelength.15nmofsacrificialoxidewasgrownandwetetchedtoremovethedamagecreatedbythedry-etchingprocessesfromthesidesurfacesofthefin.Thisstepfurtherreducesthefinthickness.Thefinalthicknessofthefinsrangedfrom15nmto30nm.2.5nmgateoxidewasgrownonthesidesurfacesofthefinat750°C.ThishighIntroductionThedouble-gateMOSFETisconsideredthemostattractivedevicetosucceedtheplanarCMOStransistorswhenthelattercannotbescaledfurther[l].TheFinFET,arecentlyreportednoveldouble-gatestructure,consistsofaverticalSifincontrolledbyself-aligneddouble-gate[2].Inspiteofitsdouble-gatestructure,theFinFETisclosetoitsroot,theconventionalMOSFETinlayoutandfabrication.Thefeaturesofthisstructureinclude(1)anultra-thinSifinforsuppressionofshort-channeleffects;(2)twogateswhichareself-alignedtoeachotherandtothesource/drain(S/D)regions;(3)raised(poly-Si)S/Dtoreduceparasiticresistance;(4)ashort(50nm)Sifinforquasi-planartopography;and(5)gate-lastprocesscompatiblewithlow-T,high-kgatedielectrics.N-channelFinFETsshowedgoodshort-channelperformancedownto17nmgatelength[3].Inthispaper,wereportP-channelFinFETresults,demonstratingthepromiseoftheFinFETstructureasafutureCMOStechnology.DeviceFabrication3.4.1IEDM99-670-7803-5410-9/99/$10.0001999IEEEFigure2:SEMtopviewaftersourceldrainetch.Athinfinisvisibleinthegapbetweensource&drainandwillbefurtherthinnedbysacrificialoxidation.Figure3:SEMtopviewafternitridespaceretch.Sifinisatthecenterofthephoto.Thegapbetweenspacersatthesidesofthefinislessthan20nm.Thisgapdefinesthegatelength.~--_-Figure4:Cross-sectionalTEMpicture:gateisdefinedbythegapbetweennitridespacers.temperaturestepcombinedwithanadditionalannealingstep,droveboronfromtheSiGeraisedS/DregionsintothefinunderneaththenitridespacerstoformP+S/Dextensions.Afterdepositing200nmofin-situ-dopedSiGe(60%Ge,withaworkfunctionof4.75eV)asthegatematerial,thegateelectrodewaspatternedandetched.Thecross-sectionalTEMpictureinFig.4showstheexcellentverticalgateandspacerprofile.ThegatelengthoftheTEMteststructure,whichisaround50nmasseeninFig.4,isdrawnlongerthanthatoftherealdevices.Finally,windowswereetchedthroughtheoxidehardmasktoallowfordirectprobingofthepoly-SiGesourceanddrainpads.Nometallizationwasusedinthisexperimenttoallowfortheoptionoffurtherthermaldrive-inannealing.DevicePerformanceFig.5showstheI-Vcharacteristicsofa18-nmgatelengthdevicewitha15nm-thickSifinbody.Idsatis288pNpmatVd=Vg=1.2V.Fig.6showstheI-Vcharacteristicsofa45-nmgatelengthdevicewitha40nm-thickSibody.Idsatis410pNpmatVd=Vg=1.2V.Inthispaper,wecountthedevicewidthastwicethefinheight.Amoreaggressivedefinitionofthe.widthofadouble-gateFETwouldhavedoubledthecurrentdensityto820pNpm.Vtroll-offcharacteristicsareshowninFig.7.VtisdefinedasthegatevoltagewhenIds=50nA/pmforVd=0.05V.Fig.8showsthesubthresholdswingdependenceongatelength.Goodshort-channelcharacteristicsareobservedforthedouble-gateFinFETstructure.Fig.9showsthel.E-02cl.E-049l.E-06l.E-083l.E-10El.E-12ULc.-n-Vd-0.05Vl.E-