VHDL语言编写BCD码60进制加法计数器

VHDL语言编写BCD码60进制加法计数器LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_ARITH.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYCNT60ISPORT(CLK,EN,CR:INSTD_LOGIC;LD:INSTD_LOGIC;D:INSTD_LOGIC_VECTOR(7DOWNTO0);CO:OUTSTD_LOGIC;Q:OUTSTD_LOGIC_VECTOR(7DOWNTO0));ENDCNT60;ARCHITECTUREaOFCNT60ISSIGNALQN:STD_LOGIC_VECTOR(7DOWNTO0);BEGINCO='1'WHEN(QN=X59ANDEN='1')ELSE'0';PROCESS(CLK,CR)BEGINIF(CR='0')THENQN=X00;ELSEIF(CLK'EVENTANDCLK='1')THENIF(LD='0')THENQN=D;ELSIF(EN='1')THENIFQN(3DOWNTO0)=9THENQN(3DOWNTO0)=0000;IFQN(7DOWNTO4)=5THENQN(7DOWNTO4)=0000;ELSEQN(7DOWNTO4)=QN(7DOWNTO4)+1;ENDIF;ELSEQN(3DOWNTO0)=QN(3DOWNTO0)+1;ENDIF;ENDIF;ENDIF;ENDIF;ENDPROCESS;Q=QN;enda;