PCB电源完整性设计用户指定

1、AllegroPCBPIUserGuideProductVersion15.7July20062001-2006CadenceDesignSystems,Inc.Allrightsreserved.PrintedintheUnitedStatesofAmerica.CadenceDesignSystems,Inc.,555RiverOaksParkway,SanJose,CA95134,USATrademarks:TrademarksandservicemarksofCadenceDesignSystems,Inc.(Cadence)containedinthisdocumentareattributedtoCadencewiththeappropriatesymbol.ForqueriesregardingCadence’strademarks,contactthecorporatelegaldepartmentattheaddressshownaboveorcall1-800-862-4522.OpenSystemC,OpenSystemCInitiative,OSCI,Sys。

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4、iatelyuponwrittennoticefromCadence.Disclaimer:InformationinthispublicationissubjecttochangewithoutnoticeanddoesnotrepresentacommitmentonthepartofCadence.TheinformationcontainedhereinistheproprietaryandconfidentialinformationofCadenceoritslicensors,andissuppliedsubjectto,andmaybeusedonlybyCadence’scustomerinaccordancewith,awrittenagreementbetweenCadenceanditscustomer.Exceptasmaybeexplicitlysetforthinsuchagreement,Cadencedoesnotmake,andexpresslydisclaims,anyrepresentationsorwarrantiesastothecomplet。

5、eness,accuracyorusefulnessoftheinformationcontainedinthisdocument.Cadencedoesnotwarrantthatuseofsuchinformationwillnotinfringeanythirdpartyrights,nordoesCadenceassumeanyliabilityfordamagesorcostsofanykindthatmayresultfromuseofsuchinformation.RestrictedRights:Use,duplication,ordisclosurebytheGovernmentissubjecttorestrictionsassetforthinFAR52.227-14andDFAR252.227-7013etseq.oritssuccessor.AllegroPCBPIUserGuideJuly20063ProductVersion15.71Introduction..................................................。

6、.......5TheChallenge:PowerIntegrityinHighSpeedPCBDesign............................................................6TheSolution:AllegroPCBPI...............................................7AllegroPCBPIWorkflow..................................................7UseModels...........................................................102PreparingforPowerplaneAnalysis.............................11UsingtheSetupWizard..................................................12InvokingtheSetupWizard.................。

7、...............................13BoardOutline..........................................................14Stack-up..............................................................15DCNet/PlaneAssociation................................................16DCPowerPairSetup....................................................19DesignDeviceSetup....................................................21LibrarySetup..........................................................223PowerIntegrityDesignandAnalysis......。

8、.....................33PowerplaneTargetImpedance............................................34Single-nodeSimulation..................................................34Analysis..............................................................40Reports..............................................................42Multi-nodeSimulation...................................................44TimeandFrequency-DomainSimulation.....................................49Multi-planePairSimulation....................。

9、...........................52AnalysisPreferences....................................................56PlacingComponents....................................................62ContentsAllegroPCBPIUserGuideJuly20064ProductVersion15.7WorkingwithVoltageRegulatorModules(VRM)...............................64PlacingNoiseSources...................................................70PlacingDecouplingCapacitors............................................72ATemporaryPackages....................................。

10、.........79Overview.............................................................80CreatingTemporarySurfaceMountedPackages..............................80CreatingTemporaryLeadedPackages......................................84AllegroPCBPIUserGuideJuly20065ProductVersion15.71IntroductionTopicsinthischapterincludeTheChallenge:PowerIntegrityinHighSpeedPCBDesignonpage6.TheSolution:AllegroPCBPIonpage7.AllegroPCBPIWorkflowonpage7.UseModelsonpage10.AllegroPCBPIUserGuideIntroductionJuly20066ProductVersi。