DDR-SDRAM-基础知识

DRAMBASICKNOWLEDGESUMMARYHulinCao–[e-mail]DRAMDeviceArchitectureDRAMAccessFlowDRAMBasicCommandsDRAMCommandSchedulePageClosePageOpenBankInterleaveCommandsRe-OrderDRAMControllerBasicDRAMControllerFunction&ArchitectureAddressMappinginDRAMControllerDRAMBASICKNOWLEDGEDRAMDeviceArchitectureDRAMAccessFlowDRAMBasicCommandsDRAMCommandSchedulePageClosePageOpenBankInterleaveCommandsRe-OrderDRAMControllerBasicDRAMControllerFunction&ArchitectureAddressMappinginDRAMControllerDRAMDEVICEARCHITECTURETypicalDRAMDeviceArchitectureSimple:1T-1CDatalosseswhenreadorover-timeDRAMDEVICEARCHITECTUREDataWidthofDRAMDeviceAlsothedatawidthofeachbankEachDRAMdevicewillhaveseveralbanksCont’dDRAMDEVICEARCHITECTUREBank?Rank?Channel?Cont’dDRAMDEVICEARCHITECTUREBankCont’dDRAMDEVICEARCHITECTURERankCont’dDRAMDEVICEARCHITECTUREChannelCont’dDRAMDEVICEARCHITECTUREOverviewofBank,Rank,ChannelCont’dDRAMDEVICEARCHITECTUREExample:TransferaCacheBlockCont’d0xFFFF…F0x000x40...64BcacheblockPhysicalmemoryspaceChannel0DIMM0Rank0DRAMDEVICEARCHITECTUREExample:TransferaCacheBlockCont’d0xFFFF…F0x000x40...64BcacheblockPhysicalmemoryspaceRank0Chip0Chip1Chip70:78:1556:63Data0:638BRow0Col0...8BDRAMDEVICEARCHITECTUREExample:TransferaCacheBlockCont’d0xFFFF…F0x000x40...64BcacheblockPhysicalmemoryspace0:78:1556:63Data0:638B8B8BRank0Chip0Chip1Chip7Row0Col1...DRAMDEVICEARCHITECTUREExample:TransferaCacheBlockCont’d0xFFFF…F0x000x40...64BcacheblockPhysicalmemoryspace0:78:1556:63Data0:638B8BRank0Chip0Chip1Chip7Row0Col1...A64Bcacheblocktakes8I/Ocyclestotransfer.Duringtheprocess,8columnsarereadsequentially.DRAMBASICKNOWLEDGEDRAMDeviceArchitectureDRAMAccessFlowDRAMBasicCommandsDRAMCommandSchedulePageClosePageOpenBankInterleaveCommandsRe-OrderDRAMControllerBasicDRAMControllerFunction&ArchitectureAddressMappinginDRAMControllerDRAMACCESSFLOWDRAMAccessFlowOverviewDRAMACCESSFLOWDifferentialSenseAmplifier–RowBufferCont’dDRAMACCESSFLOWCircuitsofDifferentialSenseAmplifierCont’dDRAMACCESSFLOWReadAccessStep1–WordLineSelectCont’dDRAMACCESSFLOWReadAccessStep2–SenseAmplifierCont’dDRAMACCESSFLOWReadAccessStep3–RestoreCont’dDRAMACCESSFLOWReadAccessStep4–Pre-chargeCont’dDRAMACCESSFLOWSenseAmplifierVoltageWaveform–ReadFlowCont’dDRAMACCESSFLOWWriteAccessFlowCont’dDRAMBASICKNOWLEDGEDRAMDeviceArchitectureDRAMAccessFlowDRAMBasicCommands&TimingParametersDRAMCommandSchedulePageClosePageOpenBankInterleaveCommandsRe-OrderDRAMControllerBasicDRAMControllerFunction&ArchitectureAddressMappinginDRAMControllerDRAMBASICCOMMANDSKeyTimingParametersParameterDescriptiontRCDRowtoColumncommandDelayTimeintervalbetweenrowaccesscommandanddatareadatsenseamplifierstRASRowAccessStrobeTimeintervalbetweenrowaccesscommandanddatarestorationinDRAMarraytCASColumnAccessStrobeTimeintervalbetweencolumnaccesscommandanddatareturnbyDRAMdevicetRPRowPrechargetimeTimeintervalthatittakesforprechargeandreadyforanotherrowaccesstWRWriteRecoverytimeMinimumtimeintervalbetweenwriteburstandprecharge,restoredatatocelltRCRowCycletimeTimeintervalbetweenaccessestodifferentrowsinagivenbanktRFCRefreshCycletimeTimeintervalbetweenrefreshcommandandactivationcommandDRAMBASICCOMMANDSRowAccessCommand–ActivationCont’dDRAMBASICCOMMANDSColumnReadCommandCont’dDRAMBASICCOMMANDSColumnWriteCommandCont’dDRAMBASICCOMMANDSPrechargeCommandCont’dDRAMBASICCOMMANDSRefreshCommandCont’dDRAMBASICCOMMANDSMoreaboutDRAMRefreshThememorycontrollerneedstorefresheachrowperiodicallytorestorechargeReadandcloseeachroweveryNmsTypicalN=64msDownsideofDRAMRefreshPowerConsumePerformancedegradationRefreshratelimitsDRAMcapacityscalingCont’dDRAMBASICCOMMANDSMoreaboutDRAMRefreshRefreshMethodBurstrefreshDistributedrefreshCont’dDRAMBASICCOMMANDSMoreaboutDRAMRefreshCont’dDRAMBASICCOMMANDSMoreaboutDRAMRefreshCont’dDRAMBASICCOMMANDSDRAMRefreshinLPDDRxTCSRTemperatureCompensatedSelfRefreshEmbeddedtemperaturesensor,adjustrefreshperiodbasedontemperature(AlsoAdoptedinDDR4)PASRPartialArraySelfRefreshOnlyusepartoftheDRAMtosavepowerCont’dDRAMBASICCOMMANDSAReadCycleCont’dDRAMBASICCOMMANDSPowerConsumeinDRAMReadCycleCont’dDRAMBASICCOMMANDSPowerRelatedTimingParameters–tRRDtRRD:RowtoRowactivationDelay,differentbankWillaffectDRAMcommandschedulingCont’dDRAMBASICCOMMANDSPowerRelatedTimingParameters–tFAWtFAW:FourBankActivationWindowWillaffectDRAMcommandschedulingCont’dDRAMBASICCOMMANDSThevalueoftRRDandtFAWisPageSizeRelatedExample:1GbitDDR2SDRAMdevicefromMicronCont’dDRAMBASICCOMMANDSTheTrendoftRRDandtFAWCont’dDRAMBASICCOMMANDStRRDandtFAWinDDR4Cont’dDRAMBASICKNOWLEDGEDRAMDeviceArchitectureDRAMAccessFlowDRAMBasicCommandsDRAMCommandSchedulePageHit/MissPageOpen/ClosePolicyBankInterleaveCommandsRe-OrderDRAMControllerBasicDRAMControllerFunction&ArchitectureAddressMappinginDRAMControllerDRAMCOMMANDSCHEDULEPage(RowBuffer)Hit/MissPageHitNextRead/WriteAccessisinthesamebank&samerowAccessFlow:Read/WriteCommandDataTransactionPageMissNextRead/WriteAccessi