VHDL数字钟设计报告

VHDL数字钟设计报告一.数字钟总体设计方案：1.1设计目的①正确显示时、分、秒；②可手动校时，能分别进行时、分的校正；③整点报时功能；1.2设计思路数字钟的设计模块包括：分频器、去抖动电路、校时电路、“时、分、秒”计数器、校时闪烁电路、整点报时和译码显示电路。每一个功能模块作为一个实体单独进行设计，最后再用VHDL的例化语句将各个模块进行整合，生成顶层实体top。该数字钟可以实现3个功能：计时功能、设置时间功能和报时功能。二．数字钟模块细节2.1分频器（fenpin）本系统共需3种频率时钟信号（1024Hz、512Hz、1Hz）。为减少输入引脚，本系统采用分频模块，只需由外部提供1024Hz基准时钟信号，其余三种频率时钟信号由分频模块得到。分频原理：为以1024Hz基准时钟经1024分频得到512Hz,1Hz频率时钟信号。分频器管脚代码：libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;useieee.std_logic_arith.all;entityfenpinisport(clk1024:instd_logic;clk1,clk512:outstd_logic);endfenpin;architecturecmloffenpinisbeginprocess(clk1024)variablecount1:integerrange0to512;variableq1:std_logic;beginifclk1024'eventandclk1024='1'thenifcount1=512thenq1:=notq1;count1:=0;elsecount1:=count1+1;endif;endif;clk1=q1;endprocess;process(clk1024)variablecount512:integerrange0to1;variableq512:std_logic;beginifclk1024'eventandclk1024='1'thenifcount512=1thenq512:=notq512;count512:=0;elsecount512:=count512+1;endif;endif;clk512=q512;endprocess;endcml;2．2校时电路（jiaoshi）本模块要实现的功能是：正常计时、校时、校分在每个状态下都会产生不同控制信号实现相应的功能。校时管脚图代码：libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entityjiaoshiisport(rst,rvs,select_rvs,mtime,mclkin,hclkin:instd_logic;hclkout,mclkout:outstd_logic);endjiaoshi;architecturecmlofjiaoshiissignalh_m:std_logic;beginp1:process(rst,rvs,hclkin,mclkin,h_m,mtime)beginifrst='0'thennull;elsifrvs='1'thenhclkout=hclkin;mclkout=mCLKin;elsifh_m='0'thenhclkout=hclkin;mclkout=mtime;elsehclkout=mtime;mclkout=mclkin;endif;endprocess;p2:process(select_rvs)beginifselect_rvs'eventandselect_rvs='1'thenh_m=noth_m;endif;endprocess;endcml;管脚图仿真图2.3时计数器（hour）分计数器(mine)秒计数器(second)时计数器管脚图时代码：libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entityhourisport(rst,hclk:instd_logic;hour0,hour1:bufferstd_logic_vector(3downto0));endhour;architecturecmlofhourisbeginprocess(rst,hclk,hour0,hour1)beginifrst='0'thenhour0=0000;hour1=0000;elsifhclk'eventandhclk='1'thenifhour0=0011andhour1=0010thenhour0=0000;hour1=0000;elsifhour0=1001thenhour0=0000;hour1=hour1+1;elsehour0=hour0+1;endif;endif;endprocess;endcml;分计数器管脚图分代码：libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entitymineisport(rst,mclk:instd_logic;mco:outstd_logic;min0,min1:bufferstd_logic_vector(3downto0));endmine;architecturecmlofmineissignalmin0_t,min1_t:std_logic_vector(3downto0);beginprocess(rst,mclk,min0,min1)beginifrst='0'thenmin0=0000;min1=0000;elsifmclk'eventandmclk='1'thenifmin0=0101andmin1=1001thenmin0=0000;min1=0000;mco='1';elsifmin0=0010andmin0=1001thenmin1=0011;min0=0000;mco='0';elsifmin0=1001thenmin1=min1+1;min0=0000;elsemin0=min0+1;endif;endif;endprocess;endcml;秒计数器管脚图秒代码：libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entitysecondisport(rst,sclk:instd_logic;sco:outstd_logic;sec0,sec1:bufferstd_logic_vector(3downto0));endsecond;architecturecmlofsecondissignalsec0_t,sec1_t:std_logic_vector(3downto0);beginprocess(rst,sclk,sec0,sec1)beginifrst='0'thensec0=0000;sec1=0000;elsifsclk'eventandsclk='1'thenifsec0=0101andsec1=1001thensec0=0000;sec1=0000;sco='1';elsifsec0=0010andsec0=1001thensec1=0011;sec0=0000;sco='0';elsifsec0=1001thensec1=sec1+1;sec0=0000;elsesec0=sec0+1;endif;endif;endprocess;endcml;2.4校时闪烁电路（flashnjiaoshi）如果正在进行校时，flashjiaoshi将实现使当前正在校时项（小时或分钟）以1Hz的频率闪烁，以便于操知道正在被校正。校时闪烁电路管脚图代码：libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entityflashjiaoshiisport(rst,sclk,rvs,select_rvs:instd_logic;hour0in,hour1in,min0in,min1in:instd_logic_vector(3downto0);hour0out,hour1out,min0out,min1out:outstd_logic_vector(3downto0));endflashjiaoshi;architecturecmlofflashjiaoshiissignalh_m:std_logic;beginp1:process(rst,sclk,rvs,hour0in,hour1in,min0in,min1in,h_m)beginifrst='0'thennull;elsifrvs='1'thenhour0out=hour0in;hour1out=hour1in;min0out=min0in;min1out=min1in;elsifh_m='0'thenhour0out=hour0in;hour1out=hour1in;ifsclk='1'thenmin0out=min0in;min1out=min1in;elsemin0out=1111;min1out=1111;endif;elsemin0out=min0in;min1out=min1in;IFsCLK='1'thenhour0out=hour0in;hour1out=hour1in;elsehour0out=1111;hour1out=1111;endif;endif;endprocessp1;p2:process(select_rvs)beginifselect_rvs'eventandselect_rvs='1'thenh_m=noth_m;endif;endprocessp2;endcml;2.5整点报时电路整点报时管脚图代码：libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entitybaoshiisport(clk1024,clk512:instd_logic;min0,min1,sec0,sec1:instd_logic_vector(3downto0);speak:outstd_logic);endbaoshi;architecturecmlofbaoshiisbeginspeak=clk512when(min1=0101andmin0=1001andsec1=0101)and(sec0=0011orsec0=0101orsec0=0111)elseclk1024when(min1=0101andmin0=1001andsec1=0101andsec0=1001)else'0';endcml;2.6译码显示电路该显示用的是动态扫描电路译码显示管脚图波形图代码：libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entityxianshiisport(clk512:instd_logic;h1,h0,m1,m0,s1,s0:instd_logic_vector(3downto0);seg7:outstd_logic_vector(6downto0);select_sig:outstd_logic_vector(5downto0));endxianshi;architecturecmlofxianshiissignaldata:std_logic_vector(3downto0);signalorder:std_logic_vector