verilog编写的1024点的fft快速傅立叶变换代码

1024点的fft快速傅立叶变换verilog代码`timescale1ns/1nsmodulecf_fft_1024_8(clock_c,enable_i,reset_i,sync_i,data_0_i,data_1_i,sync_o,data_0_o,data_1_o);inputclock_c;inputenable_i;inputreset_i;inputsync_i;input[15:0]data_0_i;input[15:0]data_1_i;outputsync_o;output[15:0]data_0_o;output[15:0]data_1_o;wiren1;wire[15:0]n2;wire[15:0]n3;cf_fft_1024_8_1s1(clock_c,sync_i,data_0_i,data_1_i,enable_i,reset_i,n1,n2,n3);assignsync_o=n1;assigndata_0_o=n2;assigndata_1_o=n3;endmodulemodulecf_fft_1024_8_1(clock_c,i1,i2,i3,i4,i5,o1,o2,o3);inputclock_c;inputi1;input[15:0]i2;input[15:0]i3;inputi4;inputi5;outputo1;output[15:0]o2;output[15:0]o3;wires1_1;wire[15:0]s1_2;wire[15:0]s1_3;wires2_1;wire[15:0]s2_2;wire[15:0]s2_3;wires3_1;wire[15:0]s3_2;wire[15:0]s3_3;wires4_1;wire[15:0]s4_2;wire[15:0]s4_3;cf_fft_1024_8_23s1(clock_c,s3_1,s3_2,s3_3,i4,i5,s1_1,s1_2,s1_3);cf_fft_1024_8_6s2(clock_c,s1_1,s1_2,s1_3,i4,i5,s2_1,s2_2,s2_3);cf_fft_1024_8_5s3(clock_c,s4_1,s4_2,s4_3,i4,i5,s3_1,s3_2,s3_3);cf_fft_1024_8_2s4(clock_c,i1,i2,i3,i4,i5,s4_1,s4_2,s4_3);assigno3=s2_3;assigno2=s2_2;assigno1=s2_1;endmodulemodulecf_fft_1024_8_2(clock_c,i1,i2,i3,i4,i5,o1,o2,o3);inputclock_c;inputi1;input[15:0]i2;input[15:0]i3;inputi4;inputi5;outputo1;output[15:0]o2;output[15:0]o3;wire[31:0]n1;wiren2;wiren3;wire[7:0]n4;wire[7:0]n5;wire[1:0]n6;wire[15:0]n7;wire[15:0]n8;wire[15:0]n9;wire[15:0]n10;wire[15:0]n11;wire[15:0]n12;wires13_1;wire[31:0]s14_1;wires15_1;wires15_2;wire[31:0]s15_3;wire[8:0]s16_1;wires16_2;assignn1={i2,i3};assignn2=s16_1[8];assignn3=~n2;assignn4={s16_1[7],s16_1[6],s16_1[5],s16_1[4],s16_1[3],s16_1[2],s16_1[1],s16_1[0]};assignn5={n4[0],n4[1],n4[2],n4[3],n4[4],n4[5],n4[6],n4[7]};assignn6={s15_2,s15_1};assignn7={s15_3[31],s15_3[30],s15_3[29],s15_3[28],s15_3[27],s15_3[26],s15_3[25],s15_3[24],s15_3[23],s15_3[22],s15_3[21],s15_3[20],s15_3[19],s15_3[18],s15_3[17],s15_3[16]};assignn8={s15_3[15],s15_3[14],s15_3[13],s15_3[12],s15_3[11],s15_3[10],s15_3[9],s15_3[8],s15_3[7],s15_3[6],s15_3[5],s15_3[4],s15_3[3],s15_3[2],s15_3[1],s15_3[0]};assignn9={s14_1[31],s14_1[30],s14_1[29],s14_1[28],s14_1[27],s14_1[26],s14_1[25],s14_1[24],s14_1[23],s14_1[22],s14_1[21],s14_1[20],s14_1[19],s14_1[18],s14_1[17],s14_1[16]};assignn10={s14_1[15],s14_1[14],s14_1[13],s14_1[12],s14_1[11],s14_1[10],s14_1[9],s14_1[8],s14_1[7],s14_1[6],s14_1[5],s14_1[4],s14_1[3],s14_1[2],s14_1[1],s14_1[0]};assignn11=s13_1?n8:n7;assignn12=s13_1?n10:n9;cf_fft_1024_8_33s13(clock_c,n6,i4,i5,s13_1);cf_fft_1024_8_4s14(clock_c,s16_2,n1,n2,n5,i4,i5,s14_1);cf_fft_1024_8_3s15(clock_c,s16_2,n1,n3,n5,i4,i5,s15_1,s15_2,s15_3);cf_fft_1024_8_24s16(clock_c,i1,i4,i5,s16_1,s16_2);assigno3=n12;assigno2=n11;assigno1=s15_1;endmodulemodulecf_fft_1024_8_3(clock_c,i1,i2,i3,i4,i5,i6,o1,o2,o3);inputclock_c;inputi1;input[31:0]i2;inputi3;input[7:0]i4;inputi5;inputi6;outputo1;outputo2;output[31:0]o3;wire[7:0]n1;wire[7:0]n2;reg[7:0]n3;wiren4;regn5;wire[7:0]n6;wiren7;wiren8;wire[31:0]n9;reg[7:0]n9a;reg[31:0]n9m[255:0];wiren10;wire[31:0]n11;reg[7:0]n11a;reg[31:0]n11m[255:0];regn12;wire[31:0]n13;wiren14;wires15_1;assignn1=8'b00000001;assignn2=n3+n1;initialn3=8'b00000000;always@(posedgeclock_c)if(n14==1'b1)n3=8'b00000000;elseif(i5==1'b1)n3=n2;assignn4=~s15_1;initialn5=1'b0;always@(posedgeclock_c)if(i6==1'b1)n5=1'b0;elseif(i5==1'b1)n5=i1;assignn6=8'b00000000;assignn7=n3==n6;assignn8=i3&n4;initialn9a=8'b00000000;always@(posedgeclock_c)if(i5==1'b1)beginif(n8==1'b1)n9m[i4]=i2;n9a=n3;endassignn9=n9m[n9a];assignn10=i3&s15_1;initialn11a=8'b00000000;always@(posedgeclock_c)if(i5==1'b1)beginif(n10==1'b1)n11m[i4]=i2;n11a=n3;endassignn11=n11m[n11a];initialn12=1'b0;always@(posedgeclock_c)if(i6==1'b1)n12=1'b0;elseif(i5==1'b1)n12=n4;assignn13=n12?n11:n9;assignn14=i1|i6;cf_fft_1024_8_30s15(clock_c,i1,i5,i6,s15_1);assigno3=n13;assigno2=n7;assigno1=n5;endmodulemodulecf_fft_1024_8_4(clock_c,i1,i2,i3,i4,i5,i6,o1);inputclock_c;inputi1;input[31:0]i2;inputi3;input[7:0]i4;inputi5;inputi6;output[31:0]o1;wire[7:0]n1;wire[7:0]n2;reg[7:0]n3;wiren4;wiren5;wire[31:0]n6;reg[7:0]n6a;reg[31:0]n6m[255:0];wiren7;wire[31:0]n8;reg[7:0]n8a;reg[31:0]n8m[255:0];regn9;wire[31:0]n10;wiren11;wires12_1;assignn1=8'b00000001;assignn2=n3+n1;initialn3=8'b00000000;always@(posedgeclock_c)if(n11==1'b1)n3=8'b00000000;elseif(i5==1'b1)n3=n2;assignn4=~s12_1;assignn5=i3&n4;initialn6a=8'b00000000;always@(posedgeclock_c)if(i5==1'b1)beginif(n5==1'b1)n6m[i4]=i2;n6a=n3;endassignn6=n6m[n6a];assignn7=i3&s12_1;initialn8a=8'b00000000;always@(posedgeclock_c)if(i5==1'b1)beginif(n7==1'b1)n8m[i4]=i2;n8a=n3;endassignn8=n8m[n8a];initialn9=1'b0;always@(posedgeclock_c)if(i6==1'b1)n9=1'b0;elseif(i5==1'b1)n9=n4;assignn10=n9?n8:n6;assignn11=i1|i6;cf_fft_1024_8_30s12(clock_c,i1,i5,i6,s12_1);assigno1=n10;endmodulemodulecf_fft_1024_8_5(clock_c,i1,i2,i3,i4,i5,o1,o2,o3);inputclock_c;inputi1;input[15:0]i2;input[15:0]i3;inputi4;inputi5;outputo1;output[15:0]o2;output[15:0]o3;wiren1;wire[31:0]n2;regn3;regn4;regn5;regn6;wire[7:0]n7;reg[7:0]n8;reg[7:0]n9;reg[7:0]n10;reg[7:0]n11;wiren12;regn13;regn14;regn15;regn16;wire