第六章CMOS组合逻辑门的设计

EE141©DigitalIntegratedCircuits2ndCombinationalCircuits1CMOS组合逻辑门设计EE141©DigitalIntegratedCircuits2ndCombinationalCircuits2组合电路与时序电路组合电路时序电路Output=f(In)Output=f(In,PreviousIn)CombinationalLogicCircuitOutInCombinationalLogicCircuitOutInStateEE141©DigitalIntegratedCircuits2ndCombinationalCircuits3静态CMOS设计在静态电路中，每一时刻每个门的输出通过一个低阻路径连到电源或地上。同时在任何时候该门的输出即为该电路实现的布尔函数值（忽略在切换期间的瞬态效应）。动态电路则依赖于把信号值暂时存放在高阻抗电路结点的电容上。EE141©DigitalIntegratedCircuits2ndCombinationalCircuits4静态互补CMOSVDDF(In1,In2,…InN)In1In2InNIn1In2InNPUNPDNPMOSonlyNMOSonlyPUN（上拉网络）和PDN（下拉网络）组成互补逻辑EE141©DigitalIntegratedCircuits2ndCombinationalCircuits5阈值对开关的影响VDDVDD0PDN0VDDCLCLPUNVDD0VDD-VTnCLVDDVDDVDD|VTp|CLSDSDVGSSSDDVGSEE141©DigitalIntegratedCircuits2ndCombinationalCircuits6NMOS管串联/并联连接一个晶体管可以看成是一个由栅信号空置的开关。当控制信号为高时NMOS开关闭合，当控制信号为低时则断开。XYABY=XifAandBXYABY=XifAORBNMOS管产生“强”0和“弱”1EE141©DigitalIntegratedCircuits2ndCombinationalCircuits7PMOS管串联/并联连接XYABY=XifAANDB=A+BXYABY=XifAORB=ABPMOS管产生“强”1和“弱”0PMOS管像一个反开关，当控制信号为低时闭合，当控制信号为高时断开。EE141©DigitalIntegratedCircuits2ndCombinationalCircuits8互补CMOS逻辑EE141©DigitalIntegratedCircuits2ndCombinationalCircuits9例:NANDEE141©DigitalIntegratedCircuits2ndCombinationalCircuits10例:NOREE141©DigitalIntegratedCircuits2ndCombinationalCircuits11复杂CMOS门OUT=D+A•(B+C)DABCDABCEE141©DigitalIntegratedCircuits2ndCombinationalCircuits12如何构成一个复杂CMOS门C(a)下拉网络SN1SN4SN2SN3DFFADBCDFABC(b)下拉网络中子网识别DAABCVDDVDDB(c)互补逻辑门EE141©DigitalIntegratedCircuits2ndCombinationalCircuits13单元设计标准单元通用逻辑能够被综合相同的高度,可变的宽度数据通道单元确定的结构(算术运算单元)包含一些连线确定的高度和宽度EE141©DigitalIntegratedCircuits2ndCombinationalCircuits14标准单元版图策略–1980s信号布线通道VDDGNDEE141©DigitalIntegratedCircuits2ndCombinationalCircuits15标准单元版图策略–1990sM2无布线通道VDDGNDM3VDDGND镜像单元镜像单元EE141©DigitalIntegratedCircuits2ndCombinationalCircuits16标准单元单元边界N阱InOutVDDGNDEE141©DigitalIntegratedCircuits2ndCombinationalCircuits17标准单元AOutVDDGNDB2输入NAND门BVDDAEE141©DigitalIntegratedCircuits2ndCombinationalCircuits18棍棒图无尺寸约束仅表示晶体管的相对位置InOutVDDGND反相器AOutVDDGNDBNAND2EE141©DigitalIntegratedCircuits2ndCombinationalCircuits19棍棒图CABX=C•(A+B)BACijABCEE141©DigitalIntegratedCircuits2ndCombinationalCircuits20两个版本的C•(A+B)XCABABCXVDDGNDVDDGNDEE141©DigitalIntegratedCircuits2ndCombinationalCircuits21棍棒图CABX=C•(A+B)BACijjVDDXXiGNDABCPUNPDNABC逻辑路径EE141©DigitalIntegratedCircuits2ndCombinationalCircuits22欧拉路径法jVDDXXiGNDABCABCEE141©DigitalIntegratedCircuits2ndCombinationalCircuits23OAI22逻辑图BADX=AB+CDBCAGNDXVDDXABDPDNPUNDCCEE141©DigitalIntegratedCircuits2ndCombinationalCircuits24例:x=ab+cdGNDxabcdVDDxGNDxabcdVDDx(a)Logicgraphsfor(ab+cd)(b)EulerPaths{abcd}acdxVDDGND(c)stickdiagramforordering{abcd}bEE141©DigitalIntegratedCircuits2ndCombinationalCircuits25多指晶体管一指两指(折叠)减少了扩散区电容EE141©DigitalIntegratedCircuits2ndCombinationalCircuits26互补CMOS特性全电压摆幅;高噪声容限逻辑功能不依赖于器件尺寸;ratioless稳定状态输出接电源或地;低输出阻抗非常高的输入阻抗;稳定状态输入电流几乎为零稳定状态电源和地之间无通路;无静态功耗传播延时与负载及输出阻抗有关EE141©DigitalIntegratedCircuits2ndCombinationalCircuits27开关延时模型AReqARpARpARnCLACLBRnARpBRpARnCintBRpARpARnBRnCLCintNAND2INVNOR2EE141©DigitalIntegratedCircuits2ndCombinationalCircuits28输入模式对延时的影响延时与输入模式有关由低到高的翻转所有输入都翻转到0–延时0.69Rp/2CL其中一个输入翻转到0–延时0.69RpCL由高到低的翻转所有输入都翻转到1–延时0.692RnCLCLBRnARpBRpARnCintEE141©DigitalIntegratedCircuits2ndCombinationalCircuits29延时与输入的关系-0.500.511.522.530100200300400A=B=10A=10,B=1A=1,B=10time[ps]Voltage[V]输入数据模式延时(psec)A=B=0167A=1,B=0164A=01,B=161A=B=1045A=1,B=1081A=10,B=180NMOS=0.5m/0.25mPMOS=0.75m/0.25mCL=100fFEE141©DigitalIntegratedCircuits2ndCombinationalCircuits30晶体管尺寸CLBRnARpBRpARnCintBRpARpARnBRnCLCint22221144EE141©DigitalIntegratedCircuits2ndCombinationalCircuits31一个复杂COMS门的尺寸OUT=D+A•(B+C)DABCDABC122244886366EE141©DigitalIntegratedCircuits2ndCombinationalCircuits32扇入（Fan-In）考虑DCBADCBACLC3C2C1分布RC模型(Elmore延时)tpHL=0.69Reqn(C1+2C2+3C3+4CL)传播延时在最坏情况下与扇入成平方关系.EE141©DigitalIntegratedCircuits2ndCombinationalCircuits33tp与扇入的关系tpLHtp(psec)fan-in扇入一般情况下不应大于4.025050075010001250246810121416tpHL平方线性tpEE141©DigitalIntegratedCircuits2ndCombinationalCircuits34tp与扇出的关系246810121416tpNOR2tp(psec)eff.fan-out所有的门有相同的驱动电流.tpNAND2tpINVSlopeisafunctionof“drivingstrength”EE141©DigitalIntegratedCircuits2ndCombinationalCircuits35tp与扇入和扇出的关系扇入:由于电阻与电容同时增加，成平方关系扇出:每增加一个额外的扇出就等于增加两个栅电容EE141©DigitalIntegratedCircuits2ndCombinationalCircuits36快速复杂CMOS门:设计技术1晶体管尺寸负载以扇出为主逐级加大晶体管的尺寸InNCLC3C2C1In1In2In3M1M2M3MN分布RC线M1M2M3…MN能够将延时降低超过20%;EE141©DigitalIntegratedCircuits2ndCombinationalCircuits37快速复杂CMOS门:设计技术2重新安排输入C2C1In1In2In3M1M2M3CLC2C1In3In2In1M1M2M3CL关键路径关键路径charged101chargedcharged1延时由CL,C1andC2的放电时间决定延时由CL的放电时间决定1101chargeddischargeddischargedEE141©DigitalIntegratedCircuits2ndCombinationalCircuits38快速复杂CMOS门:设计技术3重组逻辑结构F=ABCDEFGHEE141©DigitalIntegratedCircuits2ndCombinationalCircuits39快速复杂CMOS门:设计技术4利用BUFFER来隔离大的扇出CLCLEE141©DigitalIntegratedCircuits2ndCombinationalCircuits40快速复杂CMOS门:设计技术5降低电压摆幅线性减少功耗同时降低但后面的门会变得更慢!或者利用“灵敏放大器”将电压信号恢复(存储器设计)tpHL=0.69(3/4(CLVDD)/IDSATn)=0.69(3/4(CLVswing)/IDSATn)EE141©DigitalIntegratedCircuits2ndCombinationalCircuits41组合电路的性能通常组合