AMBAAXI4总线的研究与实现

硕士学位论文AMBAAXI4总线的研究与实现RESEARCHANDIMPLEMENTATIONOFAMBAAXI4BUS杨舜琪哈尔滨工业大学2011年12月国内图书分类号：TN47学校代码：10213国际图书分类号：621.3密级：公开工学硕士学位论文AMBAAXI4总线的研究与实现硕士研究生：杨舜琪导师：张岩教授申请学位：工学硕士学科：微电子学与固体电子学所在单位：深圳研究生院答辩日期：2011年12月授予学位单位：哈尔滨工业大学ClassifiedIndex:TN47U.D.C:621.3DissertationfortheMasterDegreeinEngineeringRESEARCHANDIMPLEMENTATIONOFAMBAAXI4BUSCandidate：ShunqiYANGSupervisor：Prof.YanZHANGAcademicDegreeAppliedfor：MasterofEngineeringSpeciality：MicroelectronicsandSolid-StateElectronicsAffiliation：ShenzhenGraduateSchoolDateofDefence：December,2011Degree-Conferring-Institution：HarbinInstituteofTechnology哈尔滨工业大学工学硕士学位论文-I-摘要随着集成电路设计复杂度的提高和产品上市时间压力的增大，基于IP核复用的SoC（SystemonChip）设计已经成为一种重要的设计方法。总线桥的设计和IP核的互连问题已经成为SoC平台中最重要的课题。IP核互连的方法，总线桥的设计以及总线协议决定了SoC平台的性能。AMBA（AdvancedMicrocontrollerBusArchitecture）总线规范由ARM公司定义。它是一组基于ARM核的SoC通信的标准协议。最新的AMBA4.0总线协议具有带宽高、延迟小和设计灵活等诸多优点，它目前已成为业界首选的高性能总线标准。本文分析并比较了Wishbone总线标准与AMBA4.0总线标准的异同。根据AMBA4.0总线标准中AXI4协议和AXI4-Lite协议，设计并实现了总线桥以及互连模块的VLSI结构。本文研究内容主要包含以下三个部分：首先，为了扩充AXI4总线可使用的IP核资源，本文设计了基于Wishbone总线和AXI4总线的总线桥IP核，包括把基于Wishbone总线的主设备集成到AXI4总线系统的WB/AXI4总线桥，把基于Wishbone总线的从设备集成到AXI4总线系统的AXI4/WB总线桥，把基于Wishbone总线的主设备集成到AXI4-Lite总线系统的WB/AXI4-Lite总线桥和把基于Wishbone总线的从设备集成到AXI4-Lite总线系统的AXI4-Lite/WB总线桥。其次，本文设计了基于AXI4总线的两种互连结构，包括交叉开关（crossbarswitch）和分享型总线（sharebus）。两种互连结构设计主要模块包括地址解码器和仲裁器。最后，本文针对设计的总线桥和互连结构，使用VerilogHDL语言进行了硬件实现，在ModelSim环境下通过了功能验证，使用ISE13.1工具进行逻辑综合，分析比较了各IP核的性能。从验证和综合来看，本文的IP设计严格遵循Wishbone总线和AMBA4.0总线的协议规范，WB/AXI4总线桥，AXI4/WB总线桥，WB/AXI4-Lite总线桥和AXI4-Lite/WB总线桥在Xilinx公司Virtex5的FPGA芯片上达到的时钟频率分别279MHz，346MHz，442MHz和427MHz，AXI4总线的交叉开关互连结构在284MHz的工作频率下，拥有22.5Gbps的数据吞吐量，AXI4总线的分享型互连结构在342MHz的工作频率下，拥有6.7Gbps的数据吞吐量，说明各IP核都具备高速的数据传输能力，完全可以胜任实际应用。关键词：互连总线；AMBAAXI4总线；Wishbone总线；协议转换哈尔滨工业大学工学硕士学位论文IIAbstractWiththeimprovementofICdesigncomplexityandmarketpressure,SoC(SystemonChip)designbasedonIPcorereusehasbecomeanimportantdesignapproach.Then,busbridgedesignandinterconnectIPcoreshavebecomethemostimportantissueinSoCplatform.InterconnectIPcore,thedesignofthebusbridgeandbusprotocoldeterminetheperformanceofSoCplatform.AMBA(AdvancedMicrocontrollerBusArchitecture)busspecificationdefinedbyARMcompanyisasetofARMcore-basedSoCcommunicationstandardprotocol.ThelatestAMBA4.0busprotocolwithhighbandwidth,lowdelayanddesignflexibilityhasbecomethechoiceofindustrystandard.ThisprojectanalyzesandcomparestheWishbonebusandAMBA4.0bus.AccordingtoAXI4protocolandAXI4-LiteprotocolofAMBA4.0busstandard,theVLSIarchitecturesofbusbridgesandinterconnectmodulesweredesignedandimplementedinthisdissertation.Thisresearchmainlyincludesthefollowingthreeparts:First,inordertoexpandtheIPcoreresourcesforAXI4bus,basedonWishbonebusandAXI4bus,thisdissertationdesignedbusbridgeIPcores,includingWB/AXI4busbridgedesignedtointegratemasterdevicesbasedonWishbonebusintoanAXI4bussystem,AXI4/WBbusbridgedesignedtointegrateslavedevicesbasedonWishbonebusintoanAXI4bussystem,WB/AXI4-LitebusbridgedesignedtointegratemasterdevicesbasedonWishbonebusintoanAXI4-Litebussystem,AXI4-Lite/WBbusbridgedesignedtointegratemasterdevicesbasedonAXI4-LitebusintoaWishbonebussystem.Secondly,thisdissertationdesignedtwointerconnectstructuresonAXI4bus,includingcross-switchandshare-bus.Bothofinterconnectstructurescontainedthemainmoduleswithaddressdecoderandarbiter.Finally,alldesignsofthebusbridgeandinterconnectarchitecturewereimplementedintohardwarebyVerilogHDLlanguageintheModelSimenvironment.TheanalysisandcomparisonfortheperformanceofallIPcoreswascompletedbylogicsynthesistools--ISE13.1.ResultsprovedthatallofIPdesignsstrictlyfollowingtheAMBA4.0busprotocolspecificationandtheWishbonebusprotocolspecification.WB/AXI4busbridge,AXI4/WBbusbridge,WB/AXI4-LitebusbridgeandAXI4-Lite/WBbusbridgereachedtheclockfrequencyof279MHz,346MHz,442MHzand427MHzunderVirtex5FPGAofXilinx,AXI4buscrossbarinterconnectstructurereachdatathroughputof22.5Gbpsattheoperatingfrequencyof284MHz,AXI4bus哈尔滨工业大学工学硕士学位论文IIIshared-businterconnectstructurereachdatathroughputof6.7Gbpsattheoperatingfrequencyof342MHz,indicatingthattheIPcoresareequippedwithhighspeedandperformancedatatransmissioncapability,fullyadoptforpracticalapplication.Keywords:Interconnectbus,AMBAAXI4,Wishbone,protocolexchange哈尔滨工业大学工学硕士学位论文III目录摘要..........................................................................................................................IABSTRACT................................................................................................................II第1章绪论...........................................................................................................11.1课题背景..................................................................................................11.2国内外相关技术发展历史和现状.............................................................11.2.1片上总线的发展........................................................................................11.2.2AMBA4.0总线产生的背景.......................................................................21.2.3AMBA4.0总线的发展趋势.......................................................................21.3本课题研究的目的及意义