基于Xilinx-FPGA高速串行接口的设计与实现毕业设计

-I-基于XilinxFPGA高速串行接口设计与实现摘要由于时钟抖动，扭曲，队列同步和串扰噪声和各种非理想因素，进一步完善面临巨大的挑战并行传输率。因此，串行传输，已成为高速数据传输系统在深亚微米主要选择。在串行传输系统为了实现高速信号传输，并可节约电能和降低成本，数据更倾向于使用低摆幅模式，LVDS和CML是低电压，小的摆动，差分信号的串行传输方式，所以它被广泛地应用于PCI。快递网络物理层和高速度SERDES电路。但这个标准的LVDS传输率只能达到3Gbps，以实现独立设计以满足5Gbps的要求及以上的高速PCI。表达应用，本文研究了伪标准的LVDS121（PLVDS）和CML的启动界面的设计研究。基于传输信号的理论，非理想因素和传输线的行为的信号完整性分析；提出了考虑高速串行传输系统的电路级和版图级设计；在PLVDS结束与CML收发器电路的设计，并提出了改进方案。其中，无歪斜单端差挠度问题提高plvds收发电路，电路的性能与加速管的改进；电平转换电路的信号快速切换到低水平的高水平，没有后续电路的调整，因此，延时小；双共模反馈电流开关电路的共模电平的控制，另一个环控制输出摆幅，输出更稳定；微分预加重技术使驱动能力强、降低码间干扰。用于CML收发器的若干关键技术，有源负反馈技术和有源电感技术不仅可以有效地扩大信号的带宽，而且可以提高电路，电路的性能，降低了电路的功耗，减少了芯片的面积；均衡技术是有效减少传输线效应符号间干扰所引起的信号失真，提高信号质量。同时也采用三级结构的樱桃。胡珀限幅放大器电路，均衡电路进一步放大到比较器输出低摆幅信号可以识别的电压幅值。在本文中，0.131cmCMOS技术实现两个PCI。表达物理层PLVD和CML高速串行数据传输接口的基础上。仿真结果表明，两种接口电路的传输速率高达5Gbps，完全符合PCIExpress表示应用要求。主题词：PLVDS，CML，预加重，均衡，有源负反馈，电压比较器，失效保护-II-Designandimplementationofhigh-speedserialinterfacebasedonXilinxFPGAAbstractDuetoclockjitter,skew,queuesynchronizationandcrosstalknoiseandvariousnon-idealfactors,paralleltransmissionratetofurtherimprovethefaceenormouschallenges.Sothattheserialtransmissionhasbecomeahigh-speeddatatransmissionsystemindeepsub-micronmainchoice.Intheserialtransmissionsysteminordertorealizethehigh-speedsignaltransmission,andcansavepowerandreducethecost,thedatatendtouselowswingmode,LVDSandCMListhelowvoltage,smallswing,differentialsignalserialtransmissionmode,sotheyarewidelyusedinPCI.ExpressnetworkphysicallayerandhighspeedSerDescircuitin.ButthisstandardLVDStransmissionratecanonlyreach3Gbps,inordertoachievetheindependentdesigntomeettherequirementsof5GbpsandabovehighspeedPCI.Expressapplication,thispaperstudiesapseudostandardLVDS121(PLVDS)andaCMLinterfacetostartthedesignresearch.Basedonthetheoryoftransmissionsignal,thesignalintegrityanalysisofnonidealfactorsandtransmissionlinebehavior;thenputforwardconsideringthehigh-speedserialtransmissionsystemcircuitlevelandlayoutleveldesign;attheendofthePLVDSandtheCMLtransceivercircuitdesignandputforwardtheimprovementscheme.Amongthem,noskewsingle-endedtodifferentialdeflectionproblemtoimprovethePLVDStransceivercircuit,thecircuitperformanceisimprovedwiththeacceleratingtube;levelconversioncircuitthesignalquicklyswitchedtoahighlevelfromlowlevel,withoutasubsequentcircuitisadjusted,therefore,thetimedelayissmall;withdoublecommon-modefeedbackcurrentswitchingcircuitinatheloopcontrolofcommonmodelevel,anotherloopcontroloutputswing,theoutputismorestable;differentialpre-emphasistechnologymakesstrongerdrivingcapabilityandreduceintersymbolinterference.SeveralkeytechnologiesusedinaCMLtransceiver,theactivenegativefeedbacktechnologyandactiveinductortechnologynotonlycaneffectivelyexpandthebandwidthofsignal,butalsocanimprovetheperformanceofcircuit,circuit,reducethepowerconsumptionofthecircuit,reducetheareaofchip;equalizationtechnologyiseffectivetoreducethetransmissionlineeffectandintersymbolinterferencecausedbysignaldistortion,thesignalqualityisimproved.AtthesametimealsousesthreelevelsofstructureofCherry.Hooperlimitingamplifiercircuit,theequalizationcircuitoutputslowswingsignalforfurtheramplificationtothecomparatorcanidentifythevoltageamplitude.Inthispaper,0.131xmCMOStechnologytoachievetwoforPCI.ExpressphysicallayerPLVDSandCMLhigh-speedserialdatatransmissioninterfacebasedon.Layoutsimulationresultsshowthat,twokindsofinterfacecircuittransmissionrateupto5Gbps,fullymeettherequirementsofPCI.Expressapplication.-III-KeyWords：PLVDS，CML，Pre—emphasis，Equalization，ActiveNegativeFeedback，LimitingAmplifier，Fail—Safe1目录摘要.....................................................................................................................................IAbstract...................................................................................................................................II引言....................................................................................................................................21绪论.........................................................................................................................................31.1课题研究背景..............................................................................................................31.2高速串行技术发展现状..............................................................................................32Virtex-5FPGA性能和设计技术.........................................................................................72.1最新款FPGA产品Virtex-5......................................................................................72.2FPGA设计方法..........................................................................................................92.3XilinxFPGA设计工具简介.......................................................................................9因为第二种方法便于改变和掌握，所以后面章节中所进行在线逻辑分析多采用第二种直接插入IP核方法进行。3基于FPGATS201链路口设计与实现................................113基于FPGATS201链路口设计与实现................................................................................123.1TS20l链路口简介.....................................................................................