超大规模集成电路2017年秋段成华老师第一次作业

Assignment1:冉文浩2017180136260161.Giveaformalordescriptivedefinitionforeachofthefollowingterms.ITRS,1Gate-Equivalent,1TechnologyNodes,1Featuresize,1ICdesigncomplexitysources,1Behavioralrepresentation,1Abstractionhierarchy,1ICdesign,1Synthesis,1Refinement,1System-levelsynthesis,1Logicsynthesis,1Layoutsynthesis,1Partialdesigntree,Designwindow,1Digitaldesignspace,1Statictiminganalysis,1Behavioralsimulation,1Postplaceandroutesimulation,1Composition-basedapproach.12.AccesstheInternetforinformationaboutDanielD.Gajski’s“Y-chart”methodologyforintegratedcircuitsdesign.Accordingtoyourinvestigationoftherelatedresearchpapersand/ortechnicalreports,pleasesummarizethe“Y-chart”theory,including(1)designrepresentationdomains,(2)designabstractionhierarchyand(3)designactivities.Referencesmustbelistedattheendofyourreport.3.WriteasummaryinChineseofthepaper“ANewEarinAdvancedICDesign”(inlessthan200characters).1.Giveaformalordescriptivedefinitionforeachofthefollowingterms.ITRS：InternationalTechnologyRoadmapforSemiconductor(国际半导体技术发展路线图)Gate-Equivalent：Agateequivalent(GE)standsforaunitofmeasurewhichallowstospecifymanufacturing-technology-independentcomplexityofdigitalelectroniccircuits.ItcorrespondstoatwoinputNANDgateTechnologyNodes：DRAM结构里第一层金属的金属间距(pitch)的一半Featuresize：roughlyhalfthelengthofthesmallesttransistor(芯片上的最小物理尺寸)ICdesigncomplexitysources:Itincludesfourmainmetrics：reliability、cost、performanceandpowerconsumption.Italsoincludesfourcomplexitysources：largesize、variabilityandreliability、powerdissipationandheterogeneity.Behavioralrepresentation:Representsadesignasablackboxanditsoutputsintermsofitsinputandtime.Indicatesnogeometricalinformationorstructureinformation.Tablestheformoftext,mathoralgorithm.Abstractionhierarchy：Abstractionhierarchiesareahumaninventiondesignedtoassistpeopleinengineeringeverycomplexsystemsbyignoringunnecessarydetails.Asetofinterrelatedrepresentationlevelsthatallowasystemtoberepresentedinvaryingamountsofdetails.Itincludessixlevels：systemlevel、chip/algorithmlevel、RTL、logicgatelevel、circuitlevel、layout/siliconlevelICdesign:Anintegratedcircuitisasetofelectroniccircuitsononesmallflatpiece(orchip)ofsemiconductormaterial,normallysilicon.(在以小片半导体材料上面设计大量的集成电路)Synthesis：将高层次的信息转换成低层次的描述，具体是指将行为域的信息转换成结构域的信息。Someofthemacro-cell(logicgate)arecompiledfromafunctionaldescription.Refinement:将行为域的信息直接转换成几何域的信息的过程。System-levelsynthesis:Mappingatasklevelspecificationontoaheterogeneoushardware/softwarearchitectureLogicsynthesis：Itisaprocessbywhichanabstractformofdesiredcircuitbehavior,typicallyatregistertransferlevel(RTL),isturnedintoadesignimplementationintermsoflogicgates,typicallybyacomputerprogramcalledasynthesistoolLayoutsynthesis:Italsocallsiliconcompiler.ItautomaticallytranslatesthefunctiondescriptionofanintegratedcircuitinaLisp-likelanguagetolayout.(将逻辑信息翻译成电路的版图信息，从而制作相应的mask板)Partialdesigntree：设计过程形成了一个部分树他的行为在不同的层级是确定的，常常在完成设计之前用来评估系统组分之间的关系。部分设计树包括自下而上和自上而下两种概念。Designwindow：Wemeanarangeoflevelsoverwhichthedesignerworksindevelopingadesign-treestructure.Digitaldesignspace:为了达到一定的客观标准，进行了分区。这些标准是设计中必须考虑的主要因素。Statictiminganalysis:静态时序分析不需要对整个电路进行仿真就能对数字电路的预期时间进行仿真模拟。Behavioralsimulation：也叫做前仿真，主要是为了验证设计逻辑，不考虑延时问题。Italsocalledagent-basedsimulation,areinstrumentalintacklingtheecologicalandinfrastructurechallengesofoursociety.Thesesimulationsallowscientiststounderstandlargecomplexsystemsuchastransportationnetwork,insectswarms,orfishschoolsbymodelingthebehaviorofmillionsifindividualagentsinsidethesystem.Postplaceandroutesimulation:后仿真和线路仿真是综合、布线以后，电路的最终形式已经固定下来，得到综合出的网表，这时在加上器件物理模型进行仿真，得到更精确的时延。在这一个步骤，确定布局后对门级电路的精确时间延迟进行重新仿真，来检查电路的时序，并对电路功能进行最后的检查。位置和线路模拟允许你去模拟一个设计的时间信息，例如门延迟信息，它可以帮助你检查出之间没有发现的错误。Composition-basedapproach：Anewcomposition-basedapproachshiftsthefocusfromcontentcreationtotheproblemsofevaluating,integrating,andverifyingmultiplepre-existingblocksandsoftwarecomponents.2.AccesstheInternetforinformationaboutDanielD.Gajski’s“Y-chart”methodologyforintegratedcircuitsdesign.Accordingtoyourinvestigationoftherelatedresearchpapersand/ortechnicalreports,pleasesummarizethe“Y-chart”theory,including(1)designrepresentationdomains,(2)designabstractionhierarchyand(3)designactivities.Referencesmustbelistedattheendofyourreport.Y-chart理论是DanielD.Gajski在1983年提出的，虽然事隔这么多年，但这个理论非常有用，他有助于帮助设计师简化集成电路的设计过程，将一个十分复杂的电路问题简化成一个相对简单的问题，在VHDL上面有着非常广泛的应用，是设计师对于抽象问题有着更清晰的认识，只要我们知道了其中某个域的某一级信息，就可以推倒到其他域的其他层的信息。改变了原先的计算机辅助设计（CAD），变成了计算机自动设计和优化版图以及连线布局，显著的提高了设计师的设计效率，对现在的设计语言产生了非常深远的影响。(1)designrepresentationdomains:ItincludesthreedomainsBehavioral(function)Representation:Representsadesignasablackboxanditsoutputsintermsofitsinputandtime.Indicatesnogeometricalinformationorstructureinformation.Takestheformoftext,mathoralgorithm.Structurerepresentation:Ablackboxisrepresentedasasetofcomponentsandconnections.Itactsasabridgebetweenfunctional(behavioral)andgeometricalrepresentation.Itdoesn’tincludephysicalinformation.Geometricalrepresentation:Itspecificssize(heightandwidth),thepositionofeachcomponent,eachportandconnectiononthesilic