数电自主实验——多功能电子表的设计与实现

Basys21.1FPGA2VerilogHDL3Basys24562.1Basys2FPGA2VerilogHDL3456ucfbit7.bit8.3.VerilogHDLRTLISEDesignSuite14.7Synthesize-XSTViewRTLSchematicViewTechnologySchematicRTLRTL4.1Basys2FPGAPC2XilinxISEDesignSuite14.73PCWin75.1Basys2Basys2led0.018led2(1)FPGAFPGAFieldProgrammableGateArrayASICFPGAVerilogVHDLFPGAICANDORXORNOTFPGAFlipflop(2)XilinxBasys2Basys2XilinxSpartan-3EFPGAAtmelAT90USBUSBISE3ISEVerilogTestFixtureparameterPERIOD=20;//50MHzalwaysbeginCLK=1'b0;#(PERIOD/2)CLK=1'b1;#(PERIOD/2);end6.1VerilogHDL2ISEDesignSuite14.7CheckSyntax34ucfucf5ISEDesignSuite14.7SynthesizeXST6RTL7ImplementDesign8GenerateProgrammingFilebit9ManageConfigurationProjectbit107.8.1.VerilogHDL23.1if2ROMMODEPCMODE39.1Basys2234510[1],,,.XilinxFPGA/CPLD[M].,2009.[2].FPGA/VHDL[M].,2011.[3]..20098-13.[4].CPLD/FPGA[M].,2010.11.[5]ReeceT,KiddieBT,RobinsonWH.IdentificationofTrojansinanFPGAusingLow-PrecisionEquipment[J].A1moduleewatch(clk,clr,digit,out1,pause,switch,led,adj);inputclk,clr,pause,adj,switch;outputdigit,out1,led;wirepause;//wire[7:6]switch;wire[3:0]adj;//adjreg[7:0]led;reg[6:0]out1;//reg[3:0]digit;//reg[31:0]count;//reg[31:0]counter;//regcn;//cn0.01reg[3:0]sec_l,sec_h,min_l,min_h,display;//initialout1=7'b0000001;initialled=8'b00000000;2always@(posedgeclk)//alwaysbegincount=count+1;//countcountercounter=counter+1;if(switch[6]==1)//switch61begin//SOSif(count==10000000)//beginled=8'b11111111;endif(count==20000000)beginled=8'b00000000;endif(count==30000000)beginled=8'b11111111;endif(count==40000000)beginled=8'b00000000;endif(count==50000000)beginled=8'b11111111;endif(count==60000000)beginled=8'b00000000;endif(count==70000000)//beginled=8'b11111111;endif(count==90000000)beginled=8'b00000000;endif(count==110000000)beginled=8'b11111111;endif(count==130000000)beginled=8'b00000000;endif(count==150000000)beginled=8'b11111111;endif(count==170000000)beginled=8'b00000000;endif(count==190000000)beginled=8'b11111111;endif(count==200000000)//beginled=8'b00000000;endif(count==210000000)beginled=8'b11111111;endif(count==220000000)beginled=8'b00000000;endif(count==230000000)beginled=8'b11111111;endif(count==240000000)beginled=8'b00000000;endif(count==300000000)begincount=0;endendelseif(switch[7]==1)//switch71beginif(clr)//begincounter=30'd0;{sec_h,sec_l}=8'h00;{min_h,min_l}=8'h00;cn=1'b0;endelseif(!pause&&{min_h,min_l,sec_h,sec_l}!=16'b0101_1001_1001_1001)if(counter=30'd499999)begincounter=30'd0;if(sec_l==9)//9beginsec_l=0;if(sec_h==9)beginsec_h=0;cn=1;endelsesec_h=sec_h+1;endelsebeginsec_l=sec_l+1;cn=0;endif(cn==1)begincn=0;if(min_l==9)beginmin_l=0;if(min_h==5);elsemin_h=min_h+1;endelsemin_l=min_l+1;endelse;endelse;endelse//awitch67beginif((count=50000000)&&(pause==0))//1beginsec_l=sec_l+1;count=0;if(sec_l==10)//101beginsec_l=0;sec_h=sec_h+1;if(sec_h==6)//61beginmin_l=min_l+1;sec_h=0;if(min_l==10)//101beginmin_h=min_h+1;min_l=0;if(min_h==6)//6min_h=0;endendendendelseif((count==25000000)&&(pause==1))//begincount=0;//if(adj[0]==1)//beginsec_l=sec_l+1;if(sec_l==10)sec_l=0;endif(adj[1]==1)//beginsec_h=sec_h+1;if(sec_h==6)sec_h=0;endif(adj[2]==1)//beginmin_l=min_l+1;if(min_l==10)min_l=0;endif(adj[3]==1)//beginmin_h=min_h+1;if(min_h==6)min_h=0;endendendend3always@(posedgeclk)begincase(count[17:16])//display2'b00:begindigit=4'b1110;display=sec_l;end2'b01:begindigit=4'b1101;display=sec_h;end2'b10:begindigit=4'b1011;display=min_l;end2'b11:begindigit=4'b0111;display=min_h;endendcaseend4always@(posedgeclk)//displayout1begincase(display)0:out1=7'b0000001;1:out1=7'b1001111;2:out1=7'b0010010;3:out1=7'b0000110;4:out1=7'b1001100;5:out1=7'b0100100;6:out1=7'b0100000;7:out1=7'b0001111;8:out1=7'b0000000;9:out1=7'b0000100;endcaseendendmoduleBUCFNETclkLOC=B8;NETclrLOC=F3;NETpauseLOC=P11;NETswitch6LOC=E2;NETswitch7LOC=N3;NETadj0LOC=G12;NETadj1LOC=C11;NETadj2LOC=M4;NETadj3LOC=A7;NETdigit3LOC=K14;NETdigit2LOC=M13;NETdigit1LOC=J12;NETdigit0LOC=F12;NETout16LOC=L14;NETout15LOC=H12;NETout14LOC=N14;NETout13LOC=N11;NETout12LOC=P12;NETout11LOC=L13;NETout10LOC=M12;NETled7LOC=G1;NETled6LOC=P4;NETled5LOC=N4;NETled4LOC=N5;NETled3LOC=P6;NETled2LOC=P7;NETled1LOC=M11;NETled0LOC=M5;