LPC1768FBD100中文资料

1.GeneraldescriptionTheLPC1768/66/65/64areARMCortex-M3basedmicrocontrollersforembeddedapplicationsfeaturingahighlevelofintegrationandlowpowerconsumption.TheARMCortex-M3isanextgenerationcorethatofferssystemenhancementssuchasenhanceddebugfeaturesandahigherlevelofsupportblockintegration.TheLPC1768/66/65/64operateatCPUfrequenciesofupto100MHz.TheARMCortex-M3CPUincorporatesa3-stagepipelineandusesaHarvardarchitecturewithseparatelocalinstructionanddatabusesaswellasathirdbusforperipherals.TheARMCortex-M3CPUalsoincludesaninternalprefetchunitthatsupportsspeculativebranching.TheperipheralcomplementoftheLPC1768/66/65/64includesupto512kBofflashmemory,upto64kBofdatamemory,EthernetMAC,USBDevice/Host/OTGinterface,8-channelgeneralpurposeDMAcontroller,4UARTs,2CANchannels,2SSPcontrollers,SPIinterface,3I2C-businterfaces,2-inputplus2-outputI2S-businterface,8-channel12-bitADC,10-bitDAC,motorcontrolPWM,QuadratureEncoderinterface,4generalpurposetimers,6-outputgeneralpurposePWM,ultra-lowpowerReal-TimeClock(RTC)withseparatebatterysupply,andupto70generalpurposeI/Opins.TheLPC1768/66/65/64arepin-compatibletothe100-pinLPC236xARM7-basedmicrocontrollerseries.2.FeaturesnARMCortex-M3processor,runningatfrequenciesofupto100MHz.AMemoryProtectionUnit(MPU)supportingeightregionsisincluded.nARMCortex-M3built-inNestedVectoredInterruptController(NVIC).nUpto512kBon-chipflashprogrammingmemory.Enhancedflashmemoryacceleratorenableshigh-speed100MHzoperationwithzerowaitstates.nIn-SystemProgramming(ISP)andIn-ApplicationProgramming(IAP)viaon-chipbootloadersoftware.nOn-chipSRAMincludes:u32/16kBofSRAMontheCPUwithlocalcode/databusforhigh-performanceCPUaccess.uTwo/one16kBSRAMblockswithseparateaccesspathsforhigherthroughput.TheseSRAMblocksmaybeusedforEthernet(LPC1768/66/64only),USB,andDMAmemory,aswellasforgeneralpurposeCPUinstructionanddatastorage.LPC1768/66/65/6432-bitARMCortex-M3microcontroller;upto512kBflashand64kBSRAMwithEthernet,USB2.0Host/Device/OTG,CANRev.02—11February2009Objectivedatasheet元器件交易网©NXPB.V.2009.Allrightsreserved.ObjectivedatasheetRev.02—11February20092of72NXPSemiconductorsLPC1768/66/65/6432-bitARMCortex-M3microcontrollernEightchannelGeneralPurposeDMAcontroller(GPDMA)ontheAHBmultilayermatrixthatcanbeusedwiththeSSP,I2S-bus,UART,theAnalog-to-DigitalandDigital-to-Analogconverterperipherals,timermatchsignals,andformemory-to-memorytransfers.nMultilayerAHBmatrixinterconnectprovidesaseparatebusforeachAHBmaster.AHBmastersincludetheCPU,GeneralPurposeDMAcontroller,EthernetMAC(LPC1768/66/64only),andtheUSBinterface.Thisinterconnectprovidescommunicationwithnoarbitrationdelays.nSplitAPBbusallowshighthroughputwithfewstallsbetweentheCPUandDMA.nSerialinterfaces:uEthernetMACwithRMIIinterfaceanddedicatedDMAcontroller(LPC1768/66/64only).uUSB2.0full-speeddevice/Host/OTGcontrollerwithdedicatedDMAcontrollerandon-chipPHYfordevice,Host,andOTGfunctions.TheLPC1764includesadevicecontrolleronly.uFourUARTswithfractionalbaudrategeneration,internalFIFO,DMAsupport,andRS-485support.OneUARThasmodemcontrolI/O,andoneUARThasIrDAsupport.uCAN2.0Bcontrollerwithtwochannels.uSPIcontrollerwithsynchronous,serial,fullduplexcommunicationandprogrammabledatalength.uTwoSSPcontrollerswithFIFOandmulti-protocolcapabilities.TheSSPinterfacescanbeusedwiththeGPDMAcontroller.uTwoI2C-businterfacessupportingfastmodewithadatarateof400kbits/swithmultipleaddressrecognitionandmonitormode.uOneI2C-businterfacesupportingfullI2C-busspecificationandfastmodepluswithadatarateof1Mbit/swithmultipleaddressrecognitionandmonitormode.uOntheLPC1768/66/65only,I2S(Inter-ICSound)interfacefordigitalaudioinputoroutput,withfractionalratecontrol.TheI2S-businterfacecanbeusedwiththeGPDMA.TheI2S-businterfacesupports3-wireand4-wiredatatransmitandreceiveaswellasmasterclockinput/output.nOtherperipherals:u70GeneralPurposeI/O(GPIO)pinswithconfigurablepull-up/downresistorsandanew,configurableopen-drainoperatingmode.u12-bitAnalog-to-DigitalConverter(ADC)withinputmultiplexingamongeightpins,conversionratesupto1MHz,andmultipleresultregisters.The12-bitADCcanbeusedwiththeGPDMAcontroller.u10-bitDigital-to-AnalogConverter(DAC)withdedicatedconversiontimerandDMAsupport(LPC1768/66/65only).uFourgeneralpurposetimers/counters,withatotalofeightcaptureinputsandtencompareoutputs.EachtimerblockhasanexternalcountinputandDMAsupport.uOnemotorcontrolPWMwithsupportforthree-phasemotorcontrol.uQuadratureencoderinterfacethatcanmonitoroneexternalquadratureencoder.uOnestandardPWM/timerblockwithexternalcountinput.uRTCwithaseparatepowerdomainanddedicatedRTCoscillator.TheRTCblockincludes64bytesofbattery-poweredbackupregisters.uWatchdogTimer(WDT)resetsthemicrocontrollerwithinareasonableamountoftimeifitentersanerroneousstate.元器件交易网©NXPB.V.2009.Allrightsreserved.ObjectivedatasheetRev.02—11February20093of72NXPSemiconductorsLPC1768/66/65/6432-bitARMCortex-M3microcontrolleruSystemticktimer,includinganexternalclockinputoption.uRepetitiveinterrupttimerprovidesprogrammableandrepeatingtimedinterrupts.uEachperipheralhasi