华信学院组成原理课设16位模型机

1石家庄经济学院华信学院计算机组成原理课程设计报告题目16位模型计算机的设计姓名学号班号指导老师成绩2015年1月2目录1.课程设计目的·····························································································22.开发工具选择·····························································································33.模型机的功能···························································································34．指令系统设计·····························································································35.数据通路设计·····························································································56.指令流程图设计··························································································67.状态转换图设计··························································································78.调试仿真····································································································89.课程设计回顾总结····················································································15参考文献·································································································151．课程设计目的（1）融会贯通计算机组成原理课程各章教学内容，通过知识综合运用，加深对CPU各模块工作原理及相互联系的认识。（2）掌握组合逻辑控制器、微程序控制器的设计。（3）理解计算机如何取出指令、如何执行指令、如何在一条指令执行结束后自动取出下一条指令并执行，牢固建立计算机整机概念。2.开发工具选择（1）硬件描述语言CPU的设计采用了功能强大的VHDL语言，它具有很强的行为能力描述，设计方法灵活，可以支持库和模块设计方法。3（2）QuartusII软件开发工具本设计采用的软件开发工具是美国的Altera公司的QuartusII，它支持多种设计输入方法，包括原理图输入、文本输入。（3）EDA实验开发系统本设计采用的EDA实验开发系统，主要用于提供可编程逻辑器件的下载电路及EDA实验开发的外围资源，供硬件验证用。3.模型机的功能内存单元addr1、addr2、result完成以下操作：[result]←[addr1]and[addr2]orimmd4.指令系统设计RAM中存放程序中的数据；ROM中存放程序中的指令，依据指令的格式将相应的指令写成二进制的机器指令存储在ROM中。实验中，指令的格式如下所示。注：操作码4位，寄存器字段rs，rt，rd各三位，Fun功能字段3位，Imm立即值字段6位；一共8个寄存器，R0只读不可写，恒为0。实验中所用指令的种类：4R类型的指令ADDRd,Rs,RtI类型的指令LWRt,Rs,immdSWRt,Rs,immdORRS,RT,immd指令操作码OP所属的指令格式Fun备注ADD0000R001R[rd]←R[rs]+R[rt]无符号加法LW0001IR[rt]←M[R[rs]+Imm]主存中内容写入寄存器SW0010IM[R[rs]+Imm]←R[rt]寄存器中内容回写到主存OR0010IR[rt]←R[rs]or[Imm]与立即数相或存放在ROM中的汇编指令,完成M[2]←M[0]andM[1]orimmdLWR1,0（R0）;R1←M[R[0]+0],由于R(0)内容为0，即R1←M[0]LWR2,1（R0）;R1←M[R[0]+1],由于R(0)内容为0，即R1←M[1]ANDR3,R1,R2;R3←R1andR2orimmdR4,imm(R3);R4←R3orimmdimmdSWR4,3(R0);M[R[0]+3]←R450LWR1,0（R0）00010000010000001LWR2,1（R0）00010000100000012ANDR3,R1,R200000010100110113orimmdR4,imm(R3)01000111000010004SWR4,3(R0)00100001000000115.数据通路设计数据存储器rsALUoutput寄存器组扩展ABmuxMuxrtPC指令寄存器J加1NPCIRrdALULMDMUX6VCCclockINPUTVCCresetINPUTstate[3..0]OUTPUTrega[15..0]OUTPUTregb[15..0]OUTPUTirout[15..0]OUTPUTaluresult[15..0]OUTPUTlmdout[15..0]OUTPUTramout[15..0]OUTPUTclkinstrin[15..0]irwrop_out[3..0]rs_out[2..0]rt_out[2..0]rd_out[2..0]func_out[2..0]immed_out[5..0]reg_irinst2RegOne[2..0]RegTwo[2..0]WriteReg[2..0]WriteData[15..0]WriteEnableclkReadOne[15..0]ReadTwo[15..0]regFileinst4clkdatain[15..0]dataout[15..0]reg_teminst6a[15..0]b[15..0]func[3..0]c[15..0]alu_16inst7clkdatain[15..0]regwrdataout[15..0]reg16inst8clkdatain[15..0]regwrdataout[15..0]reg16inst10resetclkdatain[15..0]pcwrdataout[15..0]reg_pcinstpcIn[15..0]pcVal[15..0]incpcinst13clkdatain[15..0]dataout[15..0]reg_teminst5a[15..0]b[15..0]sx[15..0]mux2inst16immed6in[5..0]extopimmed16out[15..0]immextinst17a[15..0]b[15..0]sx[15..0]mux2inst3a[2..0]b[2..0]sx[2..0]mux2_3binst18clockwrenaddress[5..0]data[15..0]q[15..0]raminst9address[5..0]q[15..0]rominst12clockresetop[3..0]func[2..0]pcwrnpcwrirwrregwraluoutregwrmemwrlmdwrregdstaluselbmemtoregsignextalufunc[3..0]present_out[3..0]controlinst14resetclockpcwrclockirwrregdstregwrclockclocksignextclockclockaluselbalufunc[3..0]memwrpcwrnpcwrirwrregwraluoutregwrmemwrlmdwrregdstaluselbmemtoregsignextalufunc[3..0]pcout[5..0]lmdwrregb[15..0]aluoutreg[5..0]irout[15..12]irout[11..9]irout[5..3]irout[2..0]immed[5..0]clockresetirout[15..12]irout[2..0]irout[15..0]memtoregaluoutregwrclockpcout[15..0]regb[15..0]aluoutreg[15..0]irout[8..6]6.指令流程图设计7:SWfinish9:finish8:immddr4:memaddr5:memfetch6:LWfinish2:rexed3:rfinish0：ifeteh1：idecodeR[rt]ALUORRLW/SWIRMIP[PC]NPCPC+1IR?AR[rs]BR[rs]ALUOALUFUNCALUOR[rd]orimmd]ALUOA+符号拓展R[rd]ALUOLW?SW?M[ALUO]BLWDM[ALUO]ALUOALUFUNCO]RtLMDPCNPCLWSW77.状态转换图设计5:memfetch3:rrfinishpcwr-=’1’;irwr=’1’;A-R[rs]B-R[rs]IR?aluselb=’0’;alufunc=aluwr=’1’;memtoreg=’0’;regdst=’1’;regwr=’1’;Segnext=’1’;aluselb=’1’;alufunc=”0100”;aluoutregwr=’1’;LW?SW?lmdwr=’1’;memwr=’0’;memtoreg=’0’;regdst=’1’;regwr=’1’;memwr=’1’;Segnext=’0’;aluselb=’1’;alufunc=”0001”;aluoutregwr=’1’;memtoreg=’0’;regdst=’0’;regwr=’1’0：ifetch1:idecode2:rrexect4:memaddr8:orimmd9:ifinish7:swfinish6:lwfinish88.调试仿真1.寄存器组图1通用寄存器组的元件图符代码:libraryieee;useieee.std_logic_1164.all;useieee.std_logic_arith.all;useieee.std_logic_unsigned.all;ENTITYregFileISport(RegOne,RegTwo,WriteReg:INSTD_LOGIC_VECTOR(2DOWNTO0);WriteData:INSTD_LOGIC_VECTOR(15DOWNTO0);WriteEnable:INSTD_LOGIC;clk:INSTD_LOGIC;ReadOne,ReadTwo:OUTSTD_LOGIC_VECTOR(15DOWNTO0));ENDENTITYregFile;ARCHITECTUREbehavOFregFileISBEGINreg:PROCESS(clk,regOne,regTwo)ISTYPEregArrayISARRAY(INTEGERRANGE0TO7)OFSTD_LOGIC_VECTOR(15downto0);VARIABLEregister_file:regArray;BEGINIF(clk'eventandclk='0')THENIF(WriteEnable='1')THENregister_file(CONV_INTEGER(