中南大学EDA课设基于verilog-的RISC-CPU设计源码

moduleRISC16(CLK,Rstn,InstAddr,Inst,DW,DAddr,WData,RData);inputCLK,Rstn;output[31:0]InstAddr,DAddr;input[15:0]Inst;outputDW;output[31:0]WData;input[31:0]RData;//IAstagereg[31:0]PC_reg;//PCregisterwire[31:0]PC_add2,PC_addoffset,PC;//newdataforPCwire[1:0]PC_Sel;//selectsignalforPCregPC_W;//writesignalforPCregister//DCstagereg[15:0]IFDC_reg;//pipelineregisterforIFDCregIFDC_W;//writesignalforIFDCregisterwireIFDC_Flush;//clearsignalforIFDCregisterreg[31:0]RegFile[31:0];//registerfilewire[31:0]Reg0,Reg1;//operand0and1reg[3:0]DC_ALU_OP;//ALUoperationcodefromdecoderregDC_WB,DC_DW,DC_LD;//writeback,store,loadsigalfromdecoderreg[3:0]DC_BJ;//branchconditionfromdecoder//EXstageregDCEX_Flush;//clearsignalforDCEXregisterreg[3:0]DCEX_ALU_OP;//ALUoperationcodeinDCEXregisterregDCEX_DW,DCEX_LD,DCEX_WB;//store,load,writebacksignalinDCEXregisterreg[31:0]DCEX_Reg0,DCEX_Reg1;//operand0,1inDCEXregisterreg[4:0]DCEX_imm,DCEX_RegAddr0,DCEX_RegAddr1;//immediatedata,registeraddress0and1inDCEXregisterwiresigned[32:0]ALU_OP0,ALU_OP1;//operand0,1forALUregsigned[32:0]ALU_Result;//resultfromALUregALU_Z,ALU_N;//flagZ,NfromALUregALU_Z_reg,ALU_N_reg;//flagregistersforZandNwire[31:0]EX_WData;//witebackdatainEXstage//WBstageregEXWB_WB;//writebacksignalinEXWBregisterreg[4:0]EXWB_WAddr;//writebackaddressinEXWBregisterreg[31:0]EXWB_WData;//writebackdatainEXWBregisterwire[31:0]EX_STData,EX_OP0,EX_OP1;//storedata,operand0and1inEXstagewire[1:0]EX_BP_Sel_MA_Addr,EX_BP_Sel_MA_Data,EX_BP_Sel_OP0,EX_BP_Sel_OP1;//bypassselectsiganls//XXstageregWBXX_WB;//writebacksignalinWBXXregisterreg[4:0]WBXX_WAddr;//writebackaddressinWBXXregisterreg[31:0]WBXX_WData;//writebackdatainWBXXregsiter////IAstage//assignPC_add2=PC_reg+2'b10;assignPC_addoffset=PC_reg+{{21{IFDC_reg[9]}},IFDC_reg[9:0],1'b0};//twodifferentway?????assignPC=(PC_Sel==2'b00)?PC_add2:(PC_Sel==2'b01)?PC_addoffset:{21'h000000,IFDC_reg[9:0],1'b0};//normalcase;branch;jump////IFstage////PCregisteralways@(posedgeCLKornegedgeRstn)beginif(!Rstn)PC_reg=32'h00000000;elseif(PC_W)PC_reg=PC;end//instructionaddressforInstRAMassignInstAddr=PC_reg;////DCstage////IFDCregisteralways@(posedgeCLKornegedgeRstn)beginif(!Rstn)IFDC_reg=16'h0000;elseif(IFDC_Flush)IFDC_reg=16'h0000;elseif(IFDC_W)IFDC_reg=Inst;end//RegFilealways@(posedgeCLK)beginif(EXWB_WB)//writesignleenableRegFile[EXWB_WAddr]=EXWB_WData;end//operand0and1fromregisterfileassignReg0=RegFile[IFDC_reg[9:5]];assignReg1=RegFile[IFDC_reg[4:0]];//decoder//DC_ALU_OP:operationcodeofALU//0000(ADD),0001(SUB,CMP),0010(AND),0011(OR),0100(XOR),0101(LSL),0110(LSR),0111(ASR),1000(MOV),1111(others)//DC_WB:writebacksiganl//DC_DW:STsignal//DC_LD:LDsignal//DC_BJ:BranchorJumpconditions//0001(BNZ),0010(BZ),0011(BLE),0100(BLT),0101(BGE),0110(BGT),0111(B),1000(JUMP),0000(others//PC_W:writeenablesigalforPC_reg//IFDC_W:writeenablesignalforIFDCpipelineregister//DCEX_Flush:clearsigalforDCEXpipelineregisteralways@(IFDC_reg[15:10])begincase(IFDC_reg[15:10])6'b010000:beginDC_ALU_OP=4'b0000;//ADDDC_WB=1'b1;DC_DW=1'b0;DC_LD=1'b0;DC_BJ=4'b0000;//noBranch,noJUMPPC_W=1'b1;IFDC_W=1'b1;DCEX_Flush=1'b0;end//**********************************************************************//PleasefinishtheRTLcodehere!//**********************************************************************//==================pc_WIFdc_wecex_flush?????6'b010001:beginDC_ALU_OP=4'b0001;//SUBDC_WB=1'b1;//resultsaveDC_DW=1'b0;//nostoreDC_LD=1'b0;//noloadDC_BJ=4'b0000;//noBranch,noJUMPPC_W=1'b1;IFDC_W=1'b1;DCEX_Flush=1'b0;end6'b010010:beginDC_ALU_OP=4'b0001;//CMPDC_WB=1'b0;//resultnosaveDC_DW=1'b0;//nostoreDC_LD=1'b0;//noloadDC_BJ=4'b0000;//noBranch,noJUMPPC_W=1'b1;IFDC_W=1'b1;DCEX_Flush=1'b0;end6'b010100:beginDC_ALU_OP=4'b0010;//ANDDC_WB=1'b1;//resultsaveDC_DW=1'b0;//nostoreDC_LD=1'b0;//noloadDC_BJ=4'b0000;//noBranch,noJUMPPC_W=1'b1;IFDC_W=1'b1;DCEX_Flush=1'b0;end6'b010101:beginDC_ALU_OP=4'b0011;//0RDC_WB=1'b1;//resultsaveDC_DW=1'b0;//nostoreDC_LD=1'b0;//noloadDC_BJ=4'b0000;//noBranch,noJUMPPC_W=1'b1;IFDC_W=1'b1;DCEX_Flush=1'b0;end6'b010110:beginDC_ALU_OP=4'b0100;//XORDC_WB=1'b1;//resultsaveDC_DW=1'b0;//nostoreDC_LD=1'b0;//noloadDC_BJ=4'b0000;//noBranch,noJUMPPC_W=1'b1;IFDC_W=1'b1;DCEX_Flush=1'b0;end6'b100000:beginDC_ALU_OP=4'b0101;//LSLDC_WB=1'b1;//resultsaveDC_DW=1'b0;//nostoreDC_LD=1'b0;//noloadDC_BJ=4'b0000;//noBranch,noJUMPPC_W=1'b1;IFDC_W=1'b1;DCEX_Flush=1'b0;end6'b100001:beginDC_ALU_OP=4'b0110;//LSRDC_WB=1'b1;//resultsaveDC_DW=1'b0;//nostoreDC_LD=1'b0;//noloadDC_BJ=4'b0000;//noBranch,noJUMPPC_W=1'b1;IFDC_W=1'b1;DCEX_Flush=1'b0;end6'b100010:beginDC_ALU_OP=4'b0111;//ASRDC_WB=1'b1;//resultsaveDC_DW=1'b0;//nostoreDC_LD=1'b0;//noloadDC_BJ=4'b0000;//noBranch,noJUMPPC_W=1'b1;IFDC_W=1'b1;DCEX_Flush=1'b0;end6'b100111:beginDC_ALU_OP=4'b1000;//MOVDC_WB=1'b1;//resultsaveDC_DW=1'b0;//nostoreDC_LD=1'b0;//noloadDC_BJ=4'b0000;//noBranch,noJUMPPC_W=1'b1;IFDC_W=1'b1;DCEX_Flush=1'b0;end6'b011000:beginDC_ALU_OP=4'b1111;//LDDC_WB=1'b1;//resultsaveDC_DW=1'b0;//nostoreDC_LD=1'b1;//loadDC_BJ=4'b0000;//noBranch,noJUMPPC_W=1'b1;IFDC_W=1'b1;DCEX_Flus