CY7C4282-25ASC中文资料

64K/128Kx9DeepSyncFIFOswithRetransmitandDepthExpansionCY7C4282CY7C4292CypressSemiconductorCorporation•3901NorthFirstStreetSanJose,CA95134408-943-2600Document#:38-06009Rev.*BRevisedAugust21,2003Features•High-speed,low-power,first-infirst-out(FIFO)memories64K×9(CY7C4282)128K×9(CY7C4292)0.5-micronCMOSforoptimumspeed/powerHigh-speed,near-zerolatency(truedual-portedmemorycell),100-MHzoperation(10-nsread/writecycletimes)Lowpower—ICC=40mA—ISB=2mAFullyasynchronousandsimultaneousreadandwriteoperationEmpty,Full,andProgrammableAlmostEmptyandAlmostFullstatusflagsTTL-compatibleRetransmitfunctionOutputEnable(OE)pinIndependentreadandwriteenablepinsSupportsfree-running50%dutycycleclockinputsWidth-ExpansionCapabilityDepth-ExpansionCapabilitythroughtoken-passingscheme(noexternallogicrequired)64-pin10×10STQFPFunctionalDescriptionTheCY7C4282/CY7C4292arehigh-speed,low-power,FIFOmemorieswithclockedreadandwriteinterfaces.Alldevicesareninebitswide.TheCY7C4282/CY7C4292canbecascadedtoincreaseFIFOdepth.ProgrammablefeaturesincludeAlmostFull/AlmostEmptyflags.TheseFIFOsprovidesolutionsforawidevarietyofdatabufferingneeds,includinghigh-speeddataacquisition,multiprocessorinterfaces,videoandcommunicationsbuffering.TheseFIFOshave9-bitinputandoutputportsthatarecontrolledbyseparateclockandenablesignals.Theinputportiscontrolledbyafree-runningclock(WCLK)andawrite-enablepin(WEN).RetransmitandSynchronousAlmostFull/AlmostEmptyflagfeaturesareavailableonthesedevices.Depthexpansionispossibleusingthecascadeinput(XI),cascadeoutput(XO),andFirstLoad(FL)pins.TheXOpinisconnectedtotheXIpinofthenextdevice,andtheXOpinofthelastdeviceshouldbeconnectedtotheXIpinofthefirstdevice.TheFLpinofthefirstdeviceistiedtoVSSandtheFLpinofalltheremainingdevicesshouldbetiedtoVCC.WhenWENisasserted,dataiswrittenintotheFIFOontherisingedgeoftheWCLKsignal.WhileWENisheldactive,dataiscontinuallywrittenintotheFIFOoneachcycle.Theoutputportiscontrolledinasimilarmannerbyafree-runningreadclock(RCLK)andareadenablepin(REN).Inaddition,theCY7C4282/92haveanoutputenablepin(OE).Thereadandwriteclocksmaybetiedtogetherforsingle-clockoperationorthetwoclocksmayberunindependentlyforasynchronousread/writeapplications.Clockfrequenciesupto100MHzareachievable.FFLogicBlockDiagramTHREE-STATEOUTPUTREGISTERREADCONTROLFLAGLOGICWRITECONTROLWRITEPOINTERREADPOINTERRESETLOGICINPUTREGISTERFLAGPROGRAMREGISTERD0-8RCLKQ0−8WENWCLKRSOEDualPortRAMArray64Kx9128Kx9RENEXPANSIONLOGICFL/RTXI/LDPAF/XOEFPAEPAF/XOCY7C4282CY7C4292Document#:38-06009Rev.*BPage2of16SelectionGuide7C4282/92-107C4282/92-157C4282/92-25UnitMaximumFrequency10066.740MHzMaximumAccessTime81015nsMinimumCycleTime101525nsMinimumDataorEnableSet-up346nsMinimumDataorEnableHold0.511nsMaximumFlagDelay81015nsActivePowerSupplyCurrent(ICC)Commercial404040mAIndustrial45CY7C4282CY7C4292Density64kx9128kx9Package64-pin10x10STQFP64-pin10x10STQFPPinConfigurationSTQFPTopView12345678910111213141548474645444342414039383736353433176418631962206121602259235824572556265527542853295230513150324916CY7C4282CY7C4292WENRSD8D7D6N/CN/CN/CN/CN/CN/CD5N/CD2D4D3Q5Q4GNDQ3Q2VCCQ1Q0GNDN/CFFOEEFN/CGNDFL/RTWCLKXI/LDGNDN/CN/CN/CN/CN/CVCCN/CN/CQ7Q8N/CGNDQ6D1D0N/CN/CN/CVCCPAF/XOPAEN/CN/CN/CN/CN/CRCLKGNDRENPinDefinitionsSignalNameDescriptionI/ODescriptionD0−8DataInputsIDataInputsfor9-bitbus.Q0−8DataOutputsODataOutputsfor9-bitbus.WENWriteEnableITheonlywriteenablewhendeviceisconfiguredtohaveprogrammableflags.DataiswrittenonaLOW-to-HIGHtransitionofWCLKwhenWENisassertedandFFisHIGH.RENReadEnableIEnablesthedeviceforReadoperation.RENmustbeassertedLOWtoallowareadoperation.WCLKWriteClockITherisingedgeclocksdataintotheFIFOwhenWENisLOWandtheFIFOisnotFull.WhenLDisasserted,WCLKwritesdataintotheprogrammableflag-offsetregister.CY7C4282CY7C4292Document#:38-06009Rev.*BPage3of16FunctionalDescription(continued)TheCY7C4282/92providesfourstatuspins:Empty,Full,ProgrammableAlmostEmpty,andProgrammableAlmostFull.TheAlmostEmpty/AlmostFullflagsareprogrammabletosinglewordgranularity.TheprogrammableflagsdefaulttoEmpty+7andFull-7.Theflagsaresynchronous,i.e.,theychangestaterelativetoeitherthereadclock(RCLK)orthewriteclock(WCLK).WhenenteringorexitingtheEmptyandAlmostEmptystates,theflagsareupdatedexclusivelybytheRCLK.TheflagsdenotingAlmostFull,andFullstatesareupdatedexclusivelybyWCLK.ThesynchronousflagarchitectureguaranteesthattheflagsmaintaintheirstatusforatleastonecycleAllconfigurationsarefabricatedusinganadvanced0.5µCMOStechnology.InputESDprotectionisgreaterthan2001V,andlatch-upispreventedbytheuseofguardrings.ArchitectureTheCY7C4282/92consistsofanarrayof64Kto128Kwordsof9bitseach(implementedbyadual-portarrayofSRAMcells),areadpointer,awritepointer,controlsignals(RCLK,WCLK,REN,WEN,RS),andflags(EF,PAE,PAF,FF).ResettingtheFIFOUponpower-up,theFIFOmustberesetwithaReset(RS)cycle.ThiscausestheFIFOtoentertheEmptyconditionsignifiedbyEFbeingLOW.Alldataoutputs(Q0−8)goLOWtRSFaftertherisingedgeofRS.InorderfortheFIFOtoresettoitsdefaultstate,theusermustnotreadorwritewhileRSisLOW.AllflagsareguaranteedtobevalidtRSFafterRSistakenLOW.