Copper-Pillar-Bump-Technology-Progress-Overview

CopperPillarBumpTechnologyProgressOverviewWeiKoh,BarryLin,JohnsonTaiPowertechTechnologyInc.,Taiwan,[e-mail]-pitchcopperpillarbump(CPB)forflipchipassemblyisexpandinginpackageapplicationsformobi!eelectronicdevicesduetotheneedforsmallerformfactor,thinthickness,andthedemandforbetterperformanceandlowerpowerconsumption.Thispaperupdatestherecenttechnologyprogressinfine-pitchcopperpillarbumpdesign,structure,fabrication,andapplicationsinflipchipandwaferlevelpackageassemblies.Withtheadventofchipscalepackages(CSP)andwaferlevelpackages(WLP),theneedforveryfine-pitchmicrobumpsbecameapparentwhenIntelfirststartedtousecopperbumpsinitsmicroprocessorpackages.TherearemanyvariantsinIP-protectedcopperpillarbumpdesigns,includingIBM'sMPS-C2(metalpostsolderchipconnection),Advanpack(APS),andIntelcoatedcopperbumps.WaferlevelprocessingstepstofabricateelectrodepositedCPBarediscussedhere.Experimentalstudiestoverifytheadvanced,fine-pitchCPBdesignusingcustomer-designeddaisychaintestvehiclewafersarepresented.Lastly,someexamplesofapplicationsofthecurrentCPBtechnologyforuseinflipchippackagesand3DICpackageintegrationusingTSV(throughsilicon.via)aredescribed.Recentreliabilityfindingsonthefine-pitchCPBarealsoincluded.IntroductionMetallicbumpinterconnectionforintegratedcircuit(IC)chipshaslongbeenrealizedasapracticaland.nece~sarymethodforhighperformance,highdatarateelectricalsignaltransmission.CopperballjointsforinterconnectwerefirstintroducedbyIBMin1969,embeddedineachterminalpadasapositivestandofftopreventsolderballcollapseinitssolidlogictechnology(SLT)semiconductordevices[1].In1970IBMfurtherdevelopedthefamouscontrolledcollapsechip'connect(C4)bumps[2,3].TheC4bumpsgainedwideacceptanceinIBMdevicesbecausethebumpscouldbeappliedtoawholewaferbyevaporationoverastencilmask.Manufacturingcost,therefore,wasalreadyakeyfactorthatC4prevailedoverthemoreexpensivecopperballjoints.Bytheearly1980s,IBMwasapplyingC4inhighperformanceserversystemswithbumppitchesabout250um.Thebumpdiametersrangedbetween100and125um;bumpheightswerebetween70and85um[4].Copper,owingtoitssuperiorelectricalandthermalproperties,isanideamaterialforflipchipbumpstoreplaceSnPborlead-freesolders.Althoughcopperballshadbeenusedforinterconnect,itismuchmoredesirabletoformtheinterconnectingbumpsinatall,slimpoststructuretonarrowthebumpfootprint.Suchtall,column-shapedpillarsarethuscalledthecopperpillarbumps(CPB).PillarBumpDesignPatentsInMay,2001,IBMwasissuedapatenthavingabumpstructureoftwolayers;thelowermetallayerhasameltingtemperatureofatleast20°Cabovetheupperlayer~old.er,henceitdoesnotfuseduringthesolderingstepandmaintatnsacertainheighttokeepthetoplayerawayfromthebumpeddevice[5].TheconstructionofthispillarbumpisillustratedinFigure1,wherethetopsolder(tin)isplatedabovethepatterningphotoresisttoformamushroomcoverbefo:ereflow.IBMcalleditspillarbumpsmetalpostsolderchipconnection(MPS-C2).In2003,anothercopperpillarbumppatentwasissuedtoFranciscaTungofAdvanpackSolutions(APS)[6].Inherpatent,Tungspecifiedaminimumcoppercolumnheightof55urnandoverallpillarbumpheightof80to120urntoreducetheeffectofthealphaparticles.Tung'sbumpstructureisverysimilartoFigure1.Fig.1IBMMPS-C2DesignYetanotherpillarbumppatentissuedtoIntelin2007describesaconductivemetalcorewhoseexteriorsurfaceiswrappedbyadiffusionbarrierlayerandasecond,externalwettinglayer[7].Ontopofthewettinglayermayresideabumplayer,suchastin.Figure2illustratestheIntelbumpconstruction.In2006,Intelshowedtheintegrationofcopperpostsonthemicroprocessordiesideasthefirststepforfirs~­levelflipchipinterconnectusingcopperpostandeutect~csolder[8].Figure3showstheIntelcopperbumpondieunderhighvolumemanufacturing,with175urnpitchandthebumpCDof105urn,Fig.2IntelBumpwithExternalCoatingoverPillar2011InternationalConferenceonElectronicPackagingTechnology&HighDensityPackaging978-1-4577-1769-7/11/$26.00©2011IEEE1133Fig.3IntelElectroplatedCopperBumpsonDieCPBAdvantagesComparedtotheconventionalC4solderballs,theCPBenjoyseveralsuperiorpropertyandstructurecharacteristicsinbumpmetallurgyandflipchipdesignselections,asshowninTable1below.Table1ComparisonbetweenCPBandC4BumpPropertyCPBC4Pitch50urn70urnConnection2000/die1000/diedensityStandoffheight30-80urn50-70urnElectricalHigherLowerconductanceThermalHigherLowerconductanceMechanicalHigheryieldLowerstrengthSelf-alignLimitedYesForflipchipandpackageassembly,thereareadditionaladvantagesinchoosingCPB;forexample:Ultra-finepitchbumpsassmallas30umstaggeredbumpsDrop-inreplacementforfinepitchsolderbumpflipchipdevicesandpackages[9]Flexiblepillarshape,size,andheightUseonflipchipdeviceexistingin-lineorstaggeredpadswithnoneedforredistributionlayer(RDL)CompatiblewithwaferlevelprocessingwithsimilarRDLandTSVfabprocesstoolsUseonICdeviceswithhighI/Ocountandhighperformance(highfrequency,bettersignalintegrity)BetterelectromigrationresistanceHigherstandofftoalloweasierunderfillcapillaryflowanduseofmoldunderfill(MUF)LoweralphaparticleeffectBetterthermalperformance,optiontoaddthermalpillarbumpsApplicationforultralowprofilepackageonpackage(PoP)However,there