用VHDL描述下列器件的功能

1．用VHDL描述下列器件的功能（1）集成移位寄存器74194（2）集成计数器74161（1）LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYS_R74194ISPORT(clrn,clk,slsi,srsi:INSTD_LOGIC;din:INSTD_LOGIC_VECTOR(3DOWNTO0);ss:INSTD_LOGIC_VECTOR(1DOWNTO0);q:OUTSTD_LOGIC_VECTOR(3DOWNTO0));ENDS_R74194;ARCHITECTUREbhvOFS_R74194ISSIGNALtmp:STD_LOGIC_VECTOR(3DOWNTO0);BEGINPROCESS(clk,clrn)BEGINIF(clrn='0')THENtmp=0000;ELSIF(clk'EVENTANDclk='1')THENIF(ss=11)THENtmp=din;ELSIF(ss=01)THENtmp=srsi&tmp(3downto1);ELSIF(ss=10)THENtmp=tmp(2downto0)&slsi;ENDIF;ENDIF;q=tmp;ENDPROCESS;ENDbhv;（2）LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYS_C74161ISPORT(clk,ldn,clrn,enp,ent:INSTD_LOGIC;din:INSTD_LOGIC_VECTOR(3DOWNTO0);q:OUTSTD_LOGIC_VECTOR(3DOWNTO0);rco:OUTSTD_LOGIC);ENDS_C74161;ARCHITECTUREbehavOFS_C74161ISSIGNALtmp:STD_LOGIC_VECTOR(3DOWNTO0);BEGINPROCESS(clk,clrn)BEGINIFclrn='0'THENtmp=0000;ELSIF(clk'EVENTANDclk='1')THENIFldn='0'THENtmp=din;ELSIF(enp='1'andent='1')THENtmp=tmp+1;ENDIF;ENDIF;q=tmp;ENDPROCESS;rco=tmp(3)andtmp(2)andtmp(1)andtmp(0)andent;ENDbehav;2.试给出一位全减器的算法描述、数据流描述、结构描述和混合描述（1）算法描述LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALLENTITYf_subISPORT(x,y,sub_in:INSTD_LOGIC;sub_out,diff:OUTSTD_LOGIC);ENDf_sub;ARCHITECTUREbhvOFf_subISSIGNALtmp:STD_LOGIC_VECTOR(2DOWNTO0);BEGINtmp=x&y&sub_in;PROCESS(tmp)BEGINCASEtmpISWHEN000=diff='0';sub_out='0';WHEN001=diff='1';sub_out='1';WHEN010=diff='1';sub_out='1';WHEN011=diff='0';sub_out='1';WHEN100=diff='1';sub_out='0';WHEN101=diff='0';sub_out='0';WHEN110=diff='0';sub_out='0';WHEN111=diff='1';sub_out='1';WHENOTHERS=NULL;ENDCASE;ENDPROCESS;ENDbhv；（2）数据流描述LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALLENTITYf_subISPORT(x,y,sub_in:INSTD_LOGIC;sub_out,diff:OUTSTD_LOGIC);ENDf_sub;ARCHITECTURErtlOFf_subISBEGINdiff=xXORyXORsub_in;sub_out=(NOTxANDy)OR((xXNORy)ANDsub_in);ENDrtl;（3）结构描述--半加器描述LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYh_subISPORT(a,b:INSTD_LOGIC;co,so:OUTSTD_LOGIC);ENDh_sub;ARCHITECTUREfh1OFh_subISBEGINso=aXORb;co=NOTaANDb;ENDfh1;--或门描述LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYor2aISPORT(a,b:INSTD_LOGIC;c:OUTSTD_LOGIC);ENDor2a;ARCHITECTUREoneOFor2aISBEGINc=aORb;ENDone;--全减器描述LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYf_sub1ISPORT(x,y,sub_in:INSTD_LOGIC;sub_out,diff:OUTSTD_LOGIC);ENDf_sub1;ARCHITECTUREstrlOFf_sub1ISCOMPONENTh_subPORT(a,b:INSTD_LOGIC;co,so:OUTSTD_LOGIC);ENDCOMPONENT;COMPONENTor2aPORT(a,b:INSTD_LOGIC;c:OUTSTD_LOGIC);ENDCOMPONENT;SIGNALd,e,f:STD_LOGIC;BEGINu1:h_subPORTMAP(x,y,d,e);u2:h_subPORTMAP(e,sub_in,f,diff);u3:or2aPORTMAP(d,f,sub_out);ENDstrl;3.用VHDL语言设计实现输出占空比为50%的1000分频器。LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYDIV_1000ISPORT(CLK,CLR:INSTD_LOGIC;DIV:OUTSTD_LOGIC);END;ARCHITECTUREAOFDIV_1000ISSIGNALQ:STD_LOGIC;BEGINDIV=Q;PROCESS(CLK,CLR)VARIABLECNT:INTEGERRANGE0TO499;BEGINIFCLR='1'THENCNT:=0;Q='0';ELSIFRISING_EDGE(CLK)THENIFCNT=499THENCNT:=0;Q=NOTQ;ELSECNT:=CNT+1;ENDIF;ENDIF;ENDPROCESS;ENDA;