ESD-class-4-ESD-protection-scheme-non-snapback-bas

Class4(1)ESDprotectionscheme–non-snapbackbased(2)ESDcurrentpathESDprotection–non-snapbackbased•Diodeunderforwardbias–Parasiticdiode–Intendeddiode•Largeenoughactivepowerclamp–Gate-coupleNMOS–Gate-drivenNMOSDiodeunderforwardbias•Lowturn-onvoltage•LargecurrentcapabilityDiodelinearregionDiodesaturationregionIVDiodeclassification•P+/N-welldiode–canbecascadedasdiodestring,butneedtonotetheDarlingtonamplificationeffect•N+/P-well(P-sub)diode•N-well/P-well(P-sub)diodeParasiticPNPinP+/N-welldiodeP+N+N-wellN+P-subDependonthewellprocess(diffusedorretrograde),thecurrentgainofparasiticPNPBJTisdifferent.•Fordiffusedwell,thecurrentgainishigh(10),andtheBJTeffectissignificant.•Forretrogradewell,thecurrentgainislow(10),andtheBJTeffectisnotsignificant.OptimumdiodelayoutAslargeperimeteraspossibleFingertypep-ringp+anoden+cathodeP+N+N-wellN+Areaindexorperimeterindex?(LVp-diodeforward)Effectofarea01000200030004000500060007000050010001500200025003000Area(um2)HBM01020304050LVpdiodemassyLVpdiodefingerLVpdiodemassyHBM/areaLVpdiodefingerHBM/area線性(LVpdiodemassy)線性(LVpdiodefinger)Effectofperi010002000300040005000600070000100200300400500600700Perimeter(um)HBM020406080100LVpdiodemassyLVpdiodefingerLVpdiodemassyHBM/periLVpdiodefingerHBM/peri線性(LVpdiodemassy)線性(LVpdiodefinger)areaperimeterAreaindexorperimeterindex?(LVp-diodereverse)Effectofarea05001000150020002500050010001500200025003000Area(um2)HBM012345LVpdiodemassyLVpdiodefingerLVpdiodemassyHBM/areaLVpdiodefingerHBM/area線性(LVpdiodemassy)線性(LVpdiodefinger)Effectofperimeter050010001500200025000100200300400500600700Perimeter(um)HBM01234567LVpdiodemassyLVpdiodefingerLVpdiodemassyHBM/periLVpdiodefingerHBM/peri線性(LVpdiodemassy)線性(LVpdiodefinger)areaperimeterTLPI-VforLVdiode(reverse)00.10.20.30.40.50.60.70.80.9105101520253035TLPvoltage(V)TLPcurrent(A)PD10x2x5PD30x2x10ND10x2x5ND30x2x10Activepowerclamp•Theadvantagesofactivepowerclamp–Uniformconductionofmulti-fingerESDdevice–CouldbeSPICEsimulated–Predictable–NostringentESD-relatedrules•Thedisadvantagesofactivepowerclamp–Largedevicesize–LargeRCtimeconstantandlargelayoutsizeKeyparametersofactivepowerESDclamp•Clampvoltage•Layoutarea•Leakagecurrentdrawnduringpower-up•QuiescentVDDtoGNDleakagecurrent•Immunitytomis-triggeringduringnormaloperationconditions•TriggertimeofpowerclampforCDMstressPopularactivepowerclampCRBIGFETCRBIGFETGate-coupledactiveclampGate-drivenactiveclampEffectofdevicewidthCR(30/0.4)*20(30/0.4)*40(30/0.4)*60(30/0.4)*120(30/0.4)*200NotenoughwidthEffectoftimeconstantR=40KΩC=0.25pFC=2.5pFC=25pFC=50pFC=100pFC=0.25pFC=2.5pFC=25pFC=50pFC=100pFCRNotenoughtimeconstantMis-triggeringunderfastpower-onpower-onramprate10n0.1u1u10u100ucurrentflowingthroughBIGFETgatepotentialofBIGFET10n0.1u1u10u100u10n0.1u1u10u100umis-triggeringDual-diode(double-diode)protectionschemePowerclampNeedtoevaluate:1.Diodeturn-onvoltage2.Diodereversefailvoltage3.Worse-casetotalvoltageduringESDdischargeDual-diode(double-diode)protectionscheme--EvaluationexamplePowerclampD1D2IVIESDVD1IVIESDVpVIVD2fRequirement:VD1+IESD*RVCC+VPVD2fRVCCRVSSPossiblecurrentpathsunder+Vssmode(3),(4):undesireddischargingpaths(1)(2)-Vss(1),(2):designeddischargingpathsInternalcircuitPowerclampI/OpadVccVss(3)(4)InternalcircuitPowerclampVccVssI/OpadPossiblecurrentpathsunder-Vddmode(1)(2)(3)(4)+Vdd(3),(4):undesireddischargingpaths(1),(2):designeddischargingpathsPowerclampVccVssI/OpadI/OpadInternalcircuitPossiblecurrentpathsunderpin-to-pintest(1)(2)(3)(3):undesireddischargingpaths(1),(2):designeddischargingpathsEffectofVSSroutingforI/OcircuitWhichisbetterforESD?Possiblecurrentpathswithseparatepowersupply—StressI/Opinvs.Vss2orVcc2:designeddischargingpathsVss2PowerclampI/OpadVcc2InternalcircuitRsubVcc1Vss1(1)(1)(+Vss),(2)(2)(+Vdd)(3)(3)(+Vss),(4)(4)(+Vdd):undesireddischargingpathsPossiblecurrentpathswithseparatepowersupply—StressVcc1vs.Vss2orVcc2:designeddischargingpathsVss2PowerclampVcc2InternalcircuitRsubVcc1Vss1(1)(1)(+Vss),(2)(+Vdd)(3)(+Vss),(4)(+Vdd):undesireddischargingpaths(4)(3)(2)Possiblecurrentpathswithback-to-backdiodeVcc1Vcc2I/OpinRsubVss2Vss1+Vssmode+VddmodeWithback-to-backdiode,theESDcurrentcandischargesafelywiththeaidofback-to-backdiode.Clampingdiodeforinter-coreinterfaceissueVss2PowerclampVcc2InternalcircuitRsubVcc1Vss1ClampingdiodeforNMOSgateClampingdiodeforPMOSgateTheeffectofinterfaceclampingdiodetVOxideBVjunctionBVTransientvoltageacrossLVgate-oxidew/odiodeTransientvoltageclampedbydiodeESDprotectionESDdeviceESDdeviceESDdeviceESDdeviceESDdeviceESDdeviceESDdeviceESDdeviceWhole-chipprotectionhavetobeconsidered.PadInternalcircuitPadInternalcircuitVcc2Vss2Vcc1Vss1Interfaceprotection