EV10AQ190

Visitourwebsite:•QuadADCwith10-bitResolutionUsinge2vProprietaryAnalogInputCross-pointSwitch–1.25GspsSamplingRateinFour-channelMode–2.5GspsSamplingRateinTwo-channelMode–5GspsSamplingRateinOne-channelMode–Built-infour-by-fourCrossPointSwitch�Single2.5GHzDifferentialSymmetricalInputClock�500mVppAnalogInput(DifferentialACorDCCoupled)�ADCMasterReset(LVDS)�DoubleDataRateOutputProtocol�LVDSOutputFormat�DigitalInterface(SPI)withResetSignal:–ChannelModeSelection–SelectableBandwidth(TwoAvailableSettings)–GainControl–OffsetControl–PhaseControl–StandbyMode(FullorPartial)–BinaryorGrayCodingSelection–TestModes(Ramp,Flashing1)�PowerSupplies:Single3.3V(1.8VOutputs)�ReducedClockInducedTransientsonPowerSupplyPinsduetoBiCMOSSiliconTechnology�PowerDissipation:1.4WperChannel�EBGA380Package(RoHS,1.27mmPitch)Performance�SelectableFullPowerInputBandwidth(–3dB)upto3.2GHz(4-2-1channelmode)�BandFlatness:0.5dBfromDCto30%ofFullPowerInputBandwidth�Channel-to-ChannelIsolation:60dB�Four-channelMode(Fsampling=1.25Gsps,–1dBFS)–Fin=100MHz(Bandwidth1GHz):ENOB=8.3bit,SFDR=62dBc,SNR=52dB,DNL=±0.3LSB,INL=±0.9LSB–Fin=620MHz(FullBandwidth):ENOB=7.7bit,SFDR=60dBc,SNR=48dB–Fin=1.2GHz(FullBandwidth):ENOB=7.2bit,SFDR=54dBc,SNR=45dB�Two-channelorone-channelmode(Fsampling=2.5or5Gsps,Fin=620MHz,–1dBFS)–Fin=620MHz(FullBandwidth):ENOB=7.6bit,SFDR=57dBc,SNR=47dB–Fin=1.2GHz(FullBandwidth):ENOB=7.2bit,SFDR=55dBc,SNR=45dB�BER:10-16atFullSpeed�Latency:Four-channel:6.5ClockCycles0952A–BDC–11/1020952A–BDC–11/10EV10AQ190e2vsemiconductorsSAS2010Applications�High-SpeedDataAcquisition�DirectRFDownConversion�UltraWidebandSatelliteDigitalReceiver�16Gbpspoint-to-pointMicrowaveReceivers�HighEnergyPhysics�AutomaticTestEquipment�High-speedTestInstrumentation�LiDAR(LightDetectionandRanging)1.BlockDiagramFigure1-1.SimplifiedBlockDiagramLVDSBuffersT/H10-bit1.25GspsADCcoreAnalogMUX(CrossPointSwitch)SerialPeripheralInterfaceOffsetGain2.5GHzclock10-bit1.25-GspsADCcore10-bit1.25GspsADCcoreLVDSBuffersLVDSBuffersLVDSBuffers10-bit1.25-GspscoreADCGainGainGainT/HT/HT/HOffsetOffsetOffsetClockBuffer++SDASelectionPhasePhasePhasePhase30952A–BDC–11/10e2vsemiconductorsSAS2010EV10AQ1902.DescriptionTheQuadADCismadeupoffour10-bitADCcoreswhichcanbeconsideredindependently(four-chan-nelmode)orgroupedby2x2cores(two-channelmodewiththeADCsinterleavedtwobytwo)orone-channelmode(whereallfourADCsareallinterleavedtogether).AllfourADCsareclockedbythesameexternalinputclocksignalandcontrolledviaanindustrystandardSPI(SerialPeripheralInterface).Ananalogmultiplexer(crosspointswitch)isusedtoselecttheanaloginputsdependingonthemodetheQuadADCisusedin.TheclockcircuitiscommontoallfourADCs.Thisblockreceivesanexternal2.5GHzclock(maximumfrequency)andpreferablyalowjittersinewavesignal.Inthisblock,theexternalclocksignalisthendividedbytwoinordertogeneratetheinternalsamplingclocks:–infour-channelmode,thesame1.25GHzclockisdirectedtoallfourADCcoresandT/H–intwo-channelmode,thein-phase1.25GHzclockissenttoADCAorCandtheinverted1.25GHzclockissenttoADCBorD,whiletheanaloginputissenttobothADCs,resultinginaninterleavedmodewithanequivalentsamplingfrequencyof2.5Gsps–inone-channelmode,thein-phase1.25GHzclockissenttoADCAwhiletheinverted1.25GHzclockissenttoADCB,thein-phase1.25GHzclockisdelayedby90degreephasetogeneratetheclockforADCCandtheinverted1.25GHzclockisdelayedby90degreephasetogeneratetheclockforADCD,resultinginaninterleavedmodewithanequivalentsamplingfrequencyof5Gsps.Note:Thisdocumentshouldbeusedinconjunctionwiththeotherdocumentationrelatingtothisproduct,forexample;Applicationnotes,Erratanotes,etc.Severaladjustmentsforthesamplingdelayandthephaseareincludedinthisclockcircuittoensureaproperphaserelationbetweenthedifferentclocksgeneratedinternallyfromthe2.5GHzclock.Thecrosspointswitch(analogMUX)iscommontoallADCs.Itallowstoselectwhichanaloginputhasbeenchosenbytheuser:–infour-channelmode,eachanaloginputissenttothecorrespondingADC(AAItoADCA,BAItoADCB,CAItoADCCandDAItoADCD)–intwo-channelmode,onecanconsiderthattherearetwoindependentADCscomposedofADCAandBforthefirstoneandofADCCandDforthesecondone;thetwoanaloginputscanbeappliedonAAIoronBAIforthefirstADC(inwhichcase,thesignalisredirectedinternallytothesecondADCofthepair;thatisBorArespectively)andonCAIorDAI(inwhichcase,thesignalisredirectedinternallytothesecondADCofthepair;thatisDorCrespectively)–inone-channelmode,oneanaloginputischosenamongAAI,BAI,CAIandDAIandthensenttoallfourADCs40952A–BDC–11/10EV10AQ190e2vsemiconductorsSAS2010Figure2-1.Four-channelModeConfigurationNote:Referto3-1”ADCTiminginFour-ChannelMode”onpage16.Figure2-2.Two-channelModeConfiguration(AnalogInputAandAnalogInputC)Referto3-2”ADCTiminginTwo-channelMode”onpage17.Figure2-3.Two-channelModeConfiguration(AnalogInputAandAnalogInputD)Pleasereferto3-2”ADCTiminginTwo-channelMode”onpage17.ADCA1.25GspsADCC1.25GspsADCD1.25GspsCLK(2.5GHz)AAI,AAINBAI,BAINCAI,CAINDAI,DAINClock1.25GHzCircuitADCBG